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5061 Guide
User manual for 5061
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Table of contents
Document Outline
1. System Overview
1.1 Power
1.2 Grounding and Power Supply Decoupling
1.3 FPGA
1.4 CS4270 Audio CODEC
1.5 CS8406 Digital Audio Transmitter
1.6 CS8416 Digital Audio Receiver
1.7 Canned Oscillator
1.8 External Control Headers
1.9 Analog Input
Figure 1. ADC THD+N
Figure 2. ADC Dynamic Range
1.10 Analog Outputs
1.11 Control Port
1.12 Hardware Mode Switches
2. FPGA Overview
2.1 FPGA Architecture
2.2 Internal Sub-Clock Routing
Figure 3. Internal Sub-Clock Routing
2.3 Internal Data Routing
Figure 4. Internal Data Routing
2.4 Internal Drivers
Figure 5. Internal Drivers
2.5 External MCLK Control
Figure 6. External MCLK Control
3. Software Mode
3.1 CDB4270 Control Scripts
3.1.1 S/PDIF In, Analog Out
3.1.2 Analog In, S/PDIF Out
3.1.3 Analog In, Analog Out (Digital Loop-Back)
3.1.4 DSP In, Analog Out
3.2 CDB4270 GUI
Figure 7. CDB4270 Controls Tab
3.3 Register Maps Control Tabs
Figure 8. Register Maps Tab - CS4270
Figure 9. Register Maps Tab - Board Configuration
Figure 10. Register Maps Tab - GPIO
4. Hardware Mode
5. FPGA GUI Register Description
5.1 FPGA REGISTER QUICK REFERENCE
5.2.1 Revision Number Bits (Bits 7:0)
Table 1. Revision Number
5.3.1 SDOUT Routing to Header (Bits 7:6)
Table 2. SDOUT Routing to Header
5.3.2 MCLK Source (Bit 4)
Table 3. MCLK Source
5.3.3 SDOUT Routing to DUT (Bits 3:2)
Table 4. SDOUT Routing to DUT
5.3.4 Subclock Routing (Bits 1:0)
Table 5. Sub-Clock Routing
5.4.1 CS8406 OMCLK Divider Control (Bits 7:6)
Table 6. CS8406 OMCLK Frequency
5.4.2 CS8406 Master/Slave Select (Bit 4)
Table 7. CS8406 Master/Slave
5.4.3 CS8406 SDIN Format Select (Bit 3)
Table 8. CS8406 SDIN Format
5.4.4 CS8406 SDIN Source (Bits 1:0)
Table 9. CS8406 SDIN Source
5.5.1 CS8416 RMCLK Divider Control (Bit 6)
Table 10. CS8416 RMCLK Frequency
5.5.2 CS8416 Master/Slave Select (Bit 4)
Table 11. CS8416 Master/Slave
5.5.3 CS8416 SDOUT Format Select (Bit 3)
Table 12. CS8416 SDOUT Format
6. CDB4270 Hardware Mode Settings
Table 13. CDB4270 Hardware Mode - Functional Description
7. CDB Connectors, Switches, Indicators and Jumpers
Table 14. Connectors and Switches
Table 15. Jumpers and Indicators
8. ADC Performance Plots
Figure 11. FFT (-1 dB 48 kHz)
Figure 12. FFT (-60 dB, 48 kHz)
Figure 13. FFT (48 kHz, No Input)
Figure 14. 48 kHz, THD+N vs. Input Freq
Figure 15. 48 kHz, THD+N vs. Level
Figure 16. 48 kHz, Fade-to-Noise Linearity
Figure 17. 48 kHz, Frequency Response
Figure 18. 48 kHz, Crosstalk
Figure 19. FFT (-1 dB 96 kHz)
Figure 20. FFT (-60 dB, 96 kHz)
Figure 21. FFT (96 kHz, No Input)
Figure 22. 96 kHz, THD+N vs. Input Freq
Figure 23. 96 kHz, THD+N vs. Level
Figure 24. 96 kHz, Fade-to-Noise Linearity
Figure 25. 96 kHz, Frequency Response
Figure 26. 96 kHz, Crosstalk
Figure 27. FFT (-1 dB 192 kHz)
Figure 28. FFT (192 kHz, -60 dB)
Figure 29. FFT (192 kHz, No Input)
Figure 30. 192 kHz, THD+N vs. Input Freq
Figure 31. 192 kHz, THD+N vs. Level
Figure 32. 192 kHz, Fade-to-Noise Linearity
Figure 33. 192 kHz, Frequency Response
Figure 34. 192 kHz, Crosstalk
9. DAC Performance Plots
Figure 35. FFT (48 kHz, 0 dB)
Figure 36. FFT (48 kHz, -60 dB)
Figure 37. FFT (48 kHz, No Input)
Figure 38. FFT (48 kHz Out-of-Band, No Input)
Figure 39. 48 kHz, THD+N vs. Input Freq
Figure 40. 48 kHz, THD+N vs. Level
Figure 41. 48 kHz, Fade-to-Noise Linearity
Figure 42. 48 kHz, Frequency Response
Figure 43. 48 kHz, Crosstalk
Figure 44. 48 kHz, Impulse Response
Figure 45. FFT (96 kHz, 0 dB)
Figure 46. FFT (96 kHz, -60 dB)
Figure 47. FFT (96 kHz, No Input)
Figure 48. FFT (96 kHz Out-of-Band, No Input)
Figure 49. 96 kHz, THD+N vs. Input Freq
Figure 50. 96 kHz, THD+N vs. Level
Figure 51. 96 kHz, Fade-to-Noise Linearity
Figure 52. 96 kHz, Frequency Response
Figure 53. 96 kHz, Crosstalk
Figure 54. 96 kHz, Impulse Response
Figure 55. FFT (192 kHz, 0 dB)
Figure 56. FFT (192 kHz, -60 dB)
Figure 57. FFT (192 kHz, No Input)
Figure 58. FFT (192 kHz Out-of-Band, No Input)
Figure 59. 192 kHz, THD+N vs. Input Freq
Figure 60. 192 kHz, THD+N vs. Level
Figure 61. 192 kHz, Fade-to-Noise Linearity
Figure 62. 192 kHz, Frequency Response
Figure 63. 192 kHz, Crosstalk
Figure 64. 192 kHz, Impulse Response
10. CDB Block Diagram
Figure 65. Block Diagram
11. CDB Schematics
Figure 66. CS4270
Figure 67. Analog Input
Figure 68. Analog Output
Figure 69. CS8406 S/PDIF Transmitter
Figure 70. CS8416 S/PDIF Receiver
Figure 71. Buffers - Clock/Data Routing
Figure 72. FPGA
Figure 73. USB/RS232 Microprocessor
Figure 74. Power
12. CDB Layout
Figure 75. Silk Screen
Figure 76. Top-Side Layer
Figure 77. Bottom-Side Layer
13. Changes Made to Rev. B Board
13.1 Modifications (Done by Cirrus Logic)
14. Revision History
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