Document Outline

• Major Revisions in This Edition
• INTRODUCTION
• CHAPTER 1 OUTLINE (uPD78078 SUBSERIES)
  • 1.1 Features
  • 1.2 Application Fields
  • 1.3 Ordering Information
  • 1.4 Quality Grade
  • 1.5 Pin Configuration (Top View)
  • 1.6 78K/0 Series Expansion
  • 1.7 Block Diagram
  • 1.8 Outline of Function
  • 1.9 Mask Options
  • 1.10 Differences with uPD78054 Subseries
• CHAPTER 2 OUTLINE (uPD78078Y SUBSERIES)
  • 2.1 Features
  • 2.2 Application Fields
  • 2.3 Ordering Information
  • 2.4 Quality Grade
  • 2.5 Pin Configuration (Top View)
  • 2.6 78K/0 Series Expansion
  • 2.7 Block Diagram
  • 2.8 Outline of Function
  • 2.9 Mask Options
  • 2.10 Differences with uPD78054Y Subseries
• CHAPTER 3 PIN FUNCTION (uPD78078 SUBSERIES)
  • 3.1 Pin Function List
    • 3.1.1 Normal operating mode pins
    • 3.1.2 PROM programming mode pins (uPD78P078 only)
  • 3.2 Description of Pin Functions
    • 3.2.1 P00 to P07 (Port 0)
    • 3.2.2 P10 to P17 (Port 1)
    • 3.2.3 P20 to P27 (Port 2)
    • 3.2.4 P30 to P37 (Port 3)
    • 3.2.5 P40 to P47 (Port 4)
    • 3.2.6 P50 to P57 (Port 5)
    • 3.2.7 P60 to P67 (Port 6)
    • 3.2.8 P70 to P72 (Port 7)
    • 3.2.9 P80 to P87 (Port 8)
    • 3.2.10 P90 to P96 (Port 9)
    • 3.2.11 P100 to P103 (Port 10)
    • 3.2.12 P120 to P127 (Port 12)
    • 3.2.13 P130 and P131 (Port 13)
    • 3.2.14 AVREF0
    • 3.2.15 AVREF1
    • 3.2.16 AVDD
    • 3.2.17 AVSS
    • 3.2.18 RESET#
    • 3.2.19 X1 and X2
    • 3.2.20 XT1 and XT2
    • 3.2.21 VDD
    • 3.2.22 VSS
    • 3.2.23 VPP (uPD78P078 only)
    • 3.2.24 IC (Mask ROM version only)
  • 3.3 Input/output Circuits and Recommended Connection of Unused Pins
• CHAPTER 4 PIN FUNCTION (uPD78078Y SUBSERIES)
  • 4.1 Pin Function List
    • 4.1.1 Normal operating mode pins
    • 4.1.2 PROM programming mode pins (uPD78P078Y only)
  • 4.2 Description of Pin Functions
    • 4.2.1 P00 to P07 (Port 0)
    • 4.2.2 P10 to P17 (Port 1)
    • 4.2.3 P20 to P27 (Port 2)
    • 4.2.4 P30 to P37 (Port 3)
    • 4.2.5 P40 to P47 (Port 4)
    • 4.2.6 P50 to P57 (Port 5)
    • 4.2.7 P60 to P67 (Port 6)
    • 4.2.8 P70 to P72 (Port 7)
    • 4.2.9 P80 to P87 (Port 8)
    • 4.2.10 P90 to P96 (Port 9)
    • 4.2.11 P100 to P103 (Port 10)
    • 4.2.12 P120 to P127 (Port 12)
    • 4.2.13 P130 and P131 (Port 13)
    • 4.2.14 AVREF0
    • 4.2.15 AVREF1
    • 4.2.16 AVDD
    • 4.2.17 AVSS
    • 4.2.18 RESET#
    • 4.2.19 X1 and X2
    • 4.2.20 XT1 and XT2
    • 4.2.21 VDD
    • 4.2.22 VSS
    • 4.2.23 VPP (uPD78P078Y only)
    • 4.2.24 IC (Mask ROM version only)
  • 4.3 Input/output Circuits and Recommended Connection of Unused Pins
• CHAPTER 5 CPU ARCHITECTURE
  • 5.1 Memory Spaces
    • 5.1.1 Internal program memory space
    • 5.1.2 Internal data memory space
    • 5.1.3 Special function register (SFR) area
    • 5.1.4 External memory space
    • 5.1.5 Data memory addressing
  • 5.2 Processor Registers
    • 5.2.1 Control registers
    • 5.2.2 General registers
    • 5.2.3 Special function register (SFR)
  • 5.3 Instruction Address Addressing
    • 5.3.1 Relative addressing
    • 5.3.2 Immediate addressing
    • 5.3.3 Table indirect addressing
    • 5.3.4 Register addressing
  • 5.4 Operand Address Addressing
    • 5.4.1 Implied addressing
    • 5.4.2 Register addressing
    • 5.4.3 Direct addressing
    • 5.4.4 Short direct addressing
    • 5.4.5 Special function register (SFR) addressing
    • 5.4.6 Register indirect addressing
    • 5.4.7 Based addressing
    • 5.4.8 Based indexed addressing
    • 5.4.9 Stack addressing
• CHAPTER 6 PORT FUNCTIONS
  • 6.1 Port Functions
  • 6.2 Port Configuration
    • 6.2.1 Port 0
    • 6.2.2 Port 1
    • 6.2.3 Port 2 (uPD78078 Subseries)
    • 6.2.4 Port 2 (uPD78078Y Subseries)
    • 6.2.5 Port 3
    • 6.2.6 Port 4
    • 6.2.7 Port 5
    • 6.2.8 Port 6
    • 6.2.9 Port 7
    • 6.2.10 Port 8
    • 6.2.11 Port 9
    • 6.2.12 Port 10
    • 6.2.13 Port 12
    • 6.2.14 Port 13
  • 6.3 Port Function Control Registers
  • 6.4 Port Function Operations
    • 6.4.1 Writing to input/output port
    • 6.4.2 Reading from input/output port
    • 6.4.3 Operations on input/output port
  • 6.5 Selection of Mask Option
• CHAPTER 7 CLOCK GENERATOR
  • 7.1 Clock Generator Functions
  • 7.2 Clock Generator Configuration
  • 7.3 Clock Generator Control Register
  • 7.4 System Clock Oscillator
    • 7.4.1 Main system clock oscillator
    • 7.4.2 Subsystem clock oscillator
    • 7.4.3 Divider
    • 7.4.4 When no subsystem clocks are used
  • 7.5 Clock Generator Operations
    • 7.5.1 Main system clock operations
    • 7.5.2 Subsystem clock operations
  • 7.6 Changing System Clock and CPU Clock Settings
    • 7.6.1 Time required for switchover between system clock and CPU clock
    • 7.6.2 System clock and CPU clock switching procedure
• CHAPTER 8 16-BIT TIMER/EVENT COUNTER
  • 8.1 Outline of Timers Incorporated into uPD78078, 78078Y Subseries
  • 8.2 16-Bit Timer/Event Counter Functions
  • 8.3 16-Bit Timer/Event Counter Configuration
  • 8.4 16-Bit Timer/Event Counter Control Registers
  • 8.5 16-Bit Timer/Event Counter Operations
    • 8.5.1 Interval timer operations
    • 8.5.2 PWM output operations
    • 8.5.3 PPG output operations
    • 8.5.4 Pulse width measurement operations
    • 8.5.5 External event counter operation
    • 8.5.6 Square-wave output operation
    • 8.5.7 One-shot pulse output operation
  • 8.6 16-Bit Timer/Event Counter Operating Precautions
• CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
  • 9.1 8-Bit Timer/Event Counters 1 and 2 Functions
    • 9.1.1 8-bit timer/event counter mode
    • 9.1.2 16-bit timer/event counter mode
  • 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations
  • 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers
  • 9.4 8-Bit Timer/Event Counters 1 and 2 Operations
    • 9.4.1 8-bit timer/event counter mode
    • 9.4.2 16-bit timer/event counter mode
  • 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions
• CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
  • 10.1 8-Bit Timer/Event Counters 5 and 6 Functions
  • 10.2 8-Bit Timer/Event Counters 5 and 6 Configurations
  • 10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers
  • 10.4 8-Bit Timer/Event Counters 5 and 6 Operations
    • 10.4.1 Interval timer operations
    • 10.4.2 External event counter operation
    • 10.4.3 Square-wave output
    • 10.4.4 PWM output operations
  • 10.5 8-Bit Timer/Event Counters 5 and 6 Precautions
• CHAPTER 11 WATCH TIMER
  • 11.1 Watch Timer Functions
  • 11.2 Watch Timer Configuration
  • 11.3 Watch Timer Control Registers
  • 11.4 Watch Timer Operations
    • 11.4.1 Watch timer operation
    • 11.4.2 Interval timer operation
• CHAPTER 12 WATCHDOG TIMER
  • 12.1 Watchdog Timer Functions
  • 12.2 Watchdog Timer Configuration
  • 12.3 Watchdog Timer Control Registers
  • 12.4 Watchdog Timer Operations
    • 12.4.1 Watchdog timer operation
    • 12.4.2 Interval timer operation
• CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT
  • 13.1 Clock Output Control Circuit Functions
  • 13.2 Clock Output Control Circuit Configuration
  • 13.3 Clock Output Function Control Registers
• CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT
  • 14.1 Buzzer Output Control Circuit Functions
  • 14.2 Buzzer Output Control Circuit Configuration
  • 14.3 Buzzer Output Function Control Registers
• CHAPTER 15 A/D CONVERTER
  • 15.1 A/D Converter Functions
  • 15.2 A/D Converter Configuration
  • 15.3 A/D Converter Control Registers
  • 15.4 A/D Converter Operations
    • 15.4.1 Basic operations of A/D converter
    • 15.4.2 Input voltage and conversion results
    • 15.4.3 A/D converter operating mode
  • 15.5 A/D Converter Cautions
• CHAPTER 16 D/A CONVERTER
  • 16.1 D/A Converter Functions
  • 16.2 D/A Converter Configuration
  • 16.3 D/A Converter Control Registers
  • 16.4 D/A Converter Operations
  • 16.5 D/A Converter Cautions
• CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (uPD78078 SUBSERIES)
  • 17.1 Serial Interface Channel 0 Functions
  • 17.2 Serial Interface Channel 0 Configuration
  • 17.3 Serial Interface Channel 0 Control Registers
  • 17.4 Serial Interface Channel 0 Operations
    • 17.4.1 Operation stop mode
    • 17.4.2 3-wire serial I/O mode operation
    • 17.4.3 SBI mode operation
    • 17.4.4 2-wire serial I/O mode operation
    • 17.4.5 SCK0#/P27 pin output manipulation
• CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (uPD78078Y Subseries)
  • 18.1 Serial Interface Channel 0 Functions
  • 18.2 Serial Interface Channel 0 Configuration
  • 18.3 Serial Interface Channel 0 Control Registers
  • 18.4 Serial Interface Channel 0 Operations
    • 18.4.1 Operation stop mode
    • 18.4.2 3-wire serial I/O mode operation
    • 18.4.3 2-wire serial I/O mode operation
    • 18.4.4 I2C bus mode operation
    • 18.4.5 Cautions on use of I2C bus mode
    • 18.4.6 Restrictions in I2C bus mode
    • 18.4.7 SCK0#/SCL/P27 pin output manipulation
• CHAPTER 19 SERIAL INTERFACE CHANNEL 1
  • 19.1 Serial Interface Channel 1 Functions
  • 19.2 Serial Interface Channel 1 Configuration
  • 19.3 Serial Interface Channel 1 Control Registers
  • 19.4 Serial Interface Channel 1 Operations
    • 19.4.1 Operation stop mode
    • 19.4.2 3-wire serial I/O mode operation
    • 19.4.3 3-wire serial I/O mode operation with automatic transmit/receive function
• CHAPTER 20 SERIAL INTERFACE CHANNEL 2
  • 20.1 Serial Interface Channel 2 Functions
  • 20.2 Serial Interface Channel 2 Configuration
  • 20.3 Serial Interface Channel 2 Control Registers
  • 20.4 Serial Interface Channel 2 Operation
    • 20.4.1 Operation stop mode
    • 20.4.2 Asynchronous serial interface (UART) mode
    • 20.4.3 3-wire serial I/O mode
    • 20.4.4 Restrictions on using UART mode
• CHAPTER 21 REAL-TIME OUTPUT PORT
  • 21.1 Real-Time Output Port Functions
  • 21.2 Real-Time Output Port Configuration
  • 21.3 Real-Time Output Port Control Registers
• CHAPTER 22 INTERRUPT FUNCTIONS
  • 22.1 Interrupt Function Types
  • 22.2 Interrupt Sources and Configuration
  • 22.3 Interrupt Function Control Registers
  • 22.4 Interrupt Servicing Operations
    • 22.4.1 Non-maskable interrupt request acknowledge operation
    • 22.4.2 Maskable interrupt request acknowledge operation
    • 22.4.3 Software interrupt request acknowledge operation
    • 22.4.4 Multiple interrupt servicing
    • 22.4.5 Interrupt request reserve
  • 22.5 Test Functions
    • 22.5.1 Registers controlling the test function
    • 22.5.2 Test input signal acknowledge operation
• CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
  • 23.1 External Device Expansion Functions
  • 23.2 External Device Expansion Function Control Register
  • 23.3 External Device Expansion Function Timing
    • 23.3.1 Timings in multiplexed bus mode
    • 23.3.2 Timings in separate bus mode
• CHAPTER 24 STANDBY FUNCTION
  • 24.1 Standby Function and Configuration
    • 24.1.1 Standby function
    • 24.1.2 Standby function control register
  • 24.2 Standby Function Operations
    • 24.2.1 HALT mode
    • 24.2.2 STOP mode
• CHAPTER 25 RESET FUNCTION
  • 25.1 Reset Function
• CHAPTER 26 ROM CORRECTION
  • 26.1 ROM Correction Functions
  • 26.2 ROM Correction Configuration
  • 26.3 ROM Correction Control Registers
  • 26.4 ROM Correction Application
  • 26.5 ROM Correction Example
  • 26.6 Program Execution Flow

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