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TESTING & ADJUSTING YOUR MVP PUMPING SYSTEM
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TESTING & ADJUSTING YOUR MVP PUMPING SYSTEM Guide
User manual for TESTING & ADJUSTING YOUR MVP PUMPING SYSTEM
Here is the user manual for TESTING & ADJUSTING YOUR MVP PUMPING SYSTEM. You can read and download this user guide for free. User's manual, provided by the manufacturer, allows you to use properly your home appliances and electronics.
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Table of contents
Document Outline
3. Applications
4. Introduction
5. Conventions
6. Pinouts
6.1 Pin Assignments
7. Register Summary
8. CPU Architecture
9. CPU Registers
9.1 Flags Register
9.1.1 Accumulator Register
9.1.2 Index Register
9.1.3 Stack Pointer Register
9.1.4 CPU Program Counter High Register
9.1.5 CPU Program Counter Low Register
9.2 Addressing Modes
9.2.1 Source Immediate
9.2.2 Source Direct
9.2.3 Source Indexed
9.2.4 Destination Direct
9.2.5 Destination Indexed
9.2.6 Destination Direct Source Immediate
9.2.7 Destination Indexed Source Immediate
9.2.8 Destination Direct Source Direct
9.2.9 Source Indirect Post Increment
9.2.10 Destination Indirect Post Increment
10. Instruction Set Summary
11. Memory Organization
11.1 Flash Program Memory Organization
11.2 Data Memory Organization
11.3 Flash
11.3.1 Flash Programming and Security
11.3.2 In-System Programming
11.4 SROM
11.4.1 Return Codes
11.5 SROM Function Descriptions
11.5.1 SWBootReset Function
11.5.2 ReadBlock Function
11.5.3 WriteBlock Function
11.5.4 EraseBlock Function
11.5.5 ProtectBlock Function
11.5.6 EraseAll Function
11.5.7 TableRead Function
11.6 SROM Table Read Description
11.6.1 Checksum Function
12. Clocking
12.1 Trim Values for the IOSCTR Register
12.2 Clock Architecture Description
12.2.1 CPU Clock
12.2.2 Interval Timer Clock (ITMRCLK)
12.2.3 Timer Capture Clock (TCAPCLK)
12.2.4 Internal Clock Trim
12.2.5 External Clock Trim
12.2.6 LPOSC Trim
12.3 CPU Clock During Sleep Mode
13. Reset
13.1 Power On Reset
13.2 Watchdog Timer Reset
14. Sleep Mode
14.1 Sleep Sequence
14.1.1 Low Power in Sleep Mode
14.2 Wakeup Sequence
15. Low Voltage Detect Control
15.1 POR Compare State
15.2 ECO Trim Register
16. General Purpose IO Ports
16.1 Port Data Registers
16.1.1 P0 Data
16.1.2 P1 Data
16.1.3 P2 Data
16.1.4 P3 Data
16.1.5 P4 Data
16.2 GPIO Port Configuration
16.2.1 Int Enable
16.2.2 Int Act Low
16.2.3 TTL Thresh
16.2.4 High Sink
16.2.5 Open Drain
16.2.6 Pull Up Enable
16.2.7 Output Enable
16.2.8 SPI Use
16.2.9 P0.0/CLKIN Configuration
16.2.10 P0.1/CLKOUT Configuration
16.2.11 P0.2/INT0-P0.4/INT2 Configuration
16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration
16.2.13 P0.7 Configuration
16.2.14 P1.0 Configuration
16.2.15 P1.1 Configuration
16.2.16 P1.2 Configuration
16.2.17 P1.3 Configuration (SSEL)
16.2.18 P1.4-P1.6 Configuration (SCLK, SMOSI, SMISO)
16.2.19 P1.7 Configuration
16.2.20 P2 Configuration
16.2.21 P3 Configuration
16.2.22 P4 Configuration
17. Serial Peripheral Interface (SPI)
17.1 SPI Data Register
17.2 SPI Configure Register
17.3 SPI Interface Pins
18. Timer Registers
18.1 Registers
18.1.1 Free Running Counter
18.1.2 Time Capture
18.1.3 Programmable Interval Timer
19. Interrupt Controller
19.1 Architectural Description
19.2 Interrupt Processing
19.3 Interrupt Latency
19.4 Interrupt Registers
19.4.1 Interrupt Clear Register
19.4.2 Interrupt Mask Registers
19.4.3 Interrupt Vector Clear Register
20. Absolute Maximum Ratings
20.1 DC Characteristics
20.2 AC Characteristics
21. Ordering Information
22. Package Handling
23. Package Diagrams
24. Document History Page
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