Document Outline

• Support
  • Worldwide Technical Support and Product Information
  • National Instruments Corporate Headquarters
  • Worldwide Offices
• Important Information
  • Warranty
  • Copyright
  • Trademarks
  • Patents
  • WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
• Compliance
• Contents
• About This Manual
  • Conventions
  • National Instruments Documentation
  • Related Documentation
• Chapter 1 Introduction
  • About the ATESeries
  • What You Need to Get Started
  • Software Programming Choices
    • NI-DAQ
      • Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and the Hardware
    • National Instruments ADE Software
    • Register-Level Programming
  • Optional Equipment
  • Custom Cabling
  • Unpacking
  • Safety Information
• Chapter 2 Installing and Configuring the Device
  • Installing the Software
  • Installing the Hardware
  • Configuring the Device
    • Bus Interface
      • Plug and Play
      • Switchless Data Acquisition
      • Base I/O Address Selection
      • DMA Channel Selection
      • Interrupt Channel Selection
      • Table 2-1. PC AT I/O Address Map
      • Table 2-2. PC AT Interrupt Assignment Map
      • Table 2-3. PC AT 16-bit DMA Channel Assignment Map
• Chapter 3 Hardware Overview
  • Figure 3-1. AT-MIO-16E-1 and AT-MIO-16E-2 Block Diagram
  • Figure 3-2. AT-MIO-64E-3 Block Diagram
  • Figure 3-3. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram
  • Figure 3-4. AT-MIO-16XE-10 Block Diagram
  • Figure 3-5. AT-AI-16XE-10 Block Diagram
  • Figure 3-6. AT-MIO-16XE-50 Block Diagram
  • Analog Input
    • Input Mode
      • Table 3-1. Available Input Configurations for the AT E Series
    • Input Polarity and Input Range
      • Table 3-2. Actual Range and Measurement Precision
      • Table 3-3. Actual Range and Measurement Precision for the AT-MIO-16XE-10, AT-AI-16XE-10...
      • Considerations for Selecting Input Ranges
    • Dither
      • Figure 3-7. Dither
    • Multiple-Channel Scanning Considerations
  • Analog Output
    • Analog Output Reference Selection
    • Analog Output Polarity Selection
    • Analog Output Reglitch Selection
  • Analog Trigger
    • Figure 3-8. Analog Trigger Block Diagram
    • Figure 3-9. Below-Low-Level Analog Triggering Mode
    • Figure 3-10. Above-High-Level Analog Triggering Mode
    • Figure 3-11. Inside-Region Analog Triggering Mode
    • Figure 3-12. High-Hysteresis Analog Triggering Mode
    • Figure 3-13. Low-Hysteresis Analog Triggering Mode
  • Digital I/O
  • Timing Signal Routing
    • Figure 3-14. CONVERT* Signal Routing
    • Programmable Function Inputs
    • Device and RTSI Clocks
    • RTSI Triggers
      • Figure 3-15. RTSI Bus Signal Connection
• Chapter 4 Connecting Signals
  • Table 4-1. I/O Connector Details
  • I/O Connector
    • Figure 4-1. I/O Connector Pin Assignment for the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10...
    • Figure 4-2. I/O Connector Pin Assignment for the AT-MIO-64E-3
    • Figure 4-3. I/O Connector Pin Assignment for the AT-MIO-16DE-10
    • I/O Connector Signal Descriptions
      • Table 4-2. I/O Signal Summary for the AT E Series
      • Table 4-3. I/O Signal Summary for the AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3
      • Table 4-4. I/O Signal Summary for the AT-MIO-16E-10 and AT-MIO-16DE-10
      • Table 4-5. I/O Signal Summary for the AT-MIO-16XE-10 and AT-AI-16XE-10
      • Table 4-6. I/O Signal Summary for the AT-MIO-16XE-50
  • Analog Input Signal Connections
    • Figure 4-4. AT E Series PGIA
  • Types of Signal Sources
    • Floating Signal Sources
    • Ground-Referenced Signal Sources
  • Input Configurations
    • Figure 4-5. Summary of Analog Input Connections
    • Differential Connection Considerations (DIFF Input Configuration)
      • Differential Connections for Ground-Referenced Signal Sources
      • Figure 4-6. Differential Input Connections for Ground-Referenced Signals
      • Differential Connections for Nonreferenced or Floating Signal Sources
      • Figure 4-7. Differential Input Connections for Nonreferenced Signals
    • Single-Ended Connection Considerations
      • Single-Ended Connections for Floating Signal Sources (RSE Configuration)
      • Figure 4-8. Single-Ended Input Connections for Nonreferenced or Floating Signals
      • Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)
      • Figure 4-9. Single-Ended Input Connections for Ground-Referenced Signal
    • Common-Mode Signal Rejection Considerations
  • Analog Output Signal Connections
    • Figure 4-10. AO Connections
  • Digital I/O Signal Connections
    • Figure 4-11. DIO Connections
  • Power Connections
  • Timing Connections
    • Figure 4-12. TIO Connections
    • Programmable Function Input Connections
    • DAQ Timing Connections
      • Figure 4-13. Typical Posttriggered Acquisition
      • Figure 4-14. Typical Pretriggered Acquisition
      • TRIG1 Signal
      • Figure 4-15. TRIG1 Input Signal Timing
      • Figure 4-16. TRIG1 Output Signal Timing
      • TRIG2 Signal
      • Figure 4-17. TRIG2 Input Signal Timing
      • Figure 4-18. TRIG2 Output Signal Timing
      • STARTSCAN Signal
      • Figure 4-19. STARTSCAN Input Signal Timing
      • Figure 4-20. STARTSCAN Output Signal Timing
      • CONVERT* Signal
      • Figure 4-21. CONVERT* Input Signal Timing
      • Figure 4-22. CONVERT* Output Signal Timing
      • AIGATE Signal
      • SISOURCE Signal
      • Figure 4-23. SISOURCE Signal Timing
      • SCANCLK Signal
      • Figure 4-24. SCANCLK Signal Timing
      • EXTSTROBE* Signal
      • Figure 4-25. EXTSTROBE* Signal Timing
    • Waveform Generation Timing Connections
      • WFTRIG Signal
      • Figure 4-26. WFTRIG Input Signal Timing
      • Figure 4-27. WFTRIG Output Signal Timing
      • UPDATE* Signal
      • Figure 4-28. UPDATE* Input Signal Timing
      • Figure 4-29. UPDATE* Output Signal Timing
      • UISOURCE Signal
      • Figure 4-30. UISOURCE Signal Timing
    • General-Purpose Timing Signal Connections
      • GPCTR0_SOURCE Signal
      • Figure 4-31. GPCTR0_SOURCE Signal Timing
      • GPCTR0_GATE Signal
      • Figure 4-32. GPCTR0_GATE Signal Timing in Edge-Detection Mode
      • GPCTR0_OUT Signal
      • Figure 4-33. GPCTR0_OUT Signal Timing
      • GPCTR0_UP_DOWN Signal
      • GPCTR1_SOURCE Signal
      • Figure 4-34. GPCTR1_SOURCE Signal Timing
      • GPCTR1_GATE Signal
      • Figure 4-35. GPCTR1_GATE Signal Timing in Edge-Detection Mode
      • GPCTR1_OUT Signal
      • Figure 4-36. GPCTR1_OUT Signal Timing
      • GPCTR1_UP_DOWN Signal
      • Figure 4-37. GPCTR Timing Summary
      • FREQ_OUT Signal
    • Timing Specifications for Digital I/O Ports A, B, and C
      • Table 4-7. Port C Signal Assignments
      • Table 4-8. Port C Signal Descriptions
      • Mode 1 Input Timing
      • Figure 4-38. Mode 1 Input Timing
      • Mode 1 Output Timing
      • Figure 4-39. Mode 1 Output Timing
      • Mode 2 Bidirectional Timing
      • Figure 4-40. Mode 2 Bidirectional Timing
  • Field Wiring Considerations
• Chapter 5 Calibrating the Device
  • Loading Calibration Constants
  • Self-Calibration
  • External Calibration
  • Other Considerations
• Appendix A Specifications
• Appendix B Optional Cable Connector Descriptions
  • Figure B-1. 68-Pin MIO Connector Pin Assignments
  • Figure B-2. 68-Pin DIO Connector Pin Assignments
  • Figure B-3. 68-Pin Extended AI Connector Pin Assignments
  • Figure B-4. 50-Pin MIO Connector Pin Assignments
  • Figure B-5. 50-Pin DIO Connector Pin Assignments
  • Figure B-6. 50-Pin Extended AI Connector Pin Assignments
• Appendix C Common Questions
  • Figure C-1. Configuring Channels for Different Acquisition Modes in LabVIEW
  • Figure C-2. Comparing Interchannel Delay and Scan Interval
  • Table C-1. Signal Name Equivalencies
• Appendix D Technical Support and Professional Services
• Glossary
  • Numbers/Symbols
  • A
  • B-D
  • E-G
  • H-L
  • M-R
  • S-U
  • V-W
• Index
  • Symbols
  • A
  • B-D
  • E-F
  • G-H
  • I-M
  • N-P
  • Q-S
  • T
  • U-W