Document Outline

• 1. Pin Configurations
  • 1.1 Pin Descriptions
• 2. Overview
  • 2.1 Block Diagram
  • 2.2 Pin Descriptions
    • 2.2.1 VCC
    • 2.2.2 GND
    • 2.2.3 Port B (PB7..PB0)
    • 2.2.4 Port C (PC7..PC0)
    • 2.2.5 Port D (PD7..PD0)
    • 2.2.6 Port E (PE2..0) RESET/ XTAL1/ XTAL2
    • 2.2.7 AVCC
    • 2.2.8 AREF
• 3. Disclaimer
• 4. Resources
• 5. About Code Examples
• 6. Data Retention
• 7. AVR CPU Core
  • 7.1 Overview
  • 7.2 ALU – Arithmetic Logic Unit
  • 7.3 Status Register
    • 7.3.1 SREG – AVR Status Register
  • 7.4 General Purpose Register File
    • 7.4.1 The X-register, Y-register, and Z-register
  • 7.5 Stack Pointer
    • 7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
  • 7.6 Instruction Execution Timing
  • 7.7 Reset and Interrupt Handling
    • 7.7.1 Interrupt Behavior
    • 7.7.2 Interrupt Response Time
• 8. Memories
  • 8.1 Overview
  • 8.2 In-System Reprogrammable Flash Program Memory
  • 8.3 SRAM Data Memory
    • 8.3.1 SRAM Data Access Times
  • 8.4 EEPROM Data Memory
    • 8.4.1 EEPROM Read/Write Access
    • 8.4.2 Preventing EEPROM Corruption
  • 8.5 I/O Memory
  • 8.6 General Purpose I/O Registers
  • 8.7 Register Description
    • 8.7.1 EEARH and EEARL – The EEPROM Address Registers
    • 8.7.2 EEDR – The EEPROM Data Register
    • 8.7.3 EECR – The EEPROM Control Register
    • 8.7.4 GPIOR0 – General Purpose I/O Register 0
    • 8.7.5 GPIOR1 – General Purpose I/O Register 1
    • 8.7.6 GPIOR2 – General Purpose I/O Register 2
• 9. System Clock and their Distribution
  • 9.1 Clock Systems and their Distribution
    • 9.1.1 CPU Clock – clkCPU
    • 9.1.2 I/O Clock – clkI/O
    • 9.1.3 Flash Clock – clkFLASH
    • 9.1.4 PLL Clock – clkPLL
    • 9.1.5 ADC Clock – clkADC
  • 9.2 Clock Sources
  • 9.3 Default Clock Source
  • 9.4 Low Power Crystal Oscillator
  • 9.5 Calibrated Internal RC Oscillator
  • 9.6 PLL
    • 9.6.1 Internal PLL
  • 9.7 128 kHz Internal Oscillator
  • 9.8 External Clock
  • 9.9 Clock Output Buffer
  • 9.10 System Clock Prescaler
  • 9.11 Register Description
    • 9.11.1 OSCCAL – Oscillator Calibration Register
    • 9.11.2 PLLCSR – PLL Control and Status Register
    • 9.11.3 CLKPR – Clock Prescaler Register
• 10. Power Management and Sleep Modes
  • 10.1 Overview
  • 10.2 Sleep Modes
  • 10.3 Idle Mode
  • 10.4 ADC Noise Reduction Mode
  • 10.5 Power-down Mode
  • 10.6 Standby Mode
  • 10.7 Power Reduction Register
  • 10.8 Minimizing Power Consumption
    • 10.8.1 Analog to Digital Converter
    • 10.8.2 Analog Comparator
    • 10.8.3 Brown-out Detector
    • 10.8.4 Internal Voltage Reference
    • 10.8.5 Watchdog Timer
    • 10.8.6 Port Pins
    • 10.8.7 On-chip Debug System
  • 10.9 Register Description
    • 10.9.1 SMCR – Sleep Mode Control Register
    • 10.9.2 PRR – Power Reduction Register
• 11. System Control and Reset
  • 11.1 Resetting the AVR
  • 11.2 Reset Sources
    • 11.2.1 Power-on Reset
    • 11.2.2 External Reset
    • 11.2.3 Brown-out Detection
    • 11.2.4 Watchdog Reset
  • 11.3 Internal Voltage Reference
    • 11.3.1 Voltage Reference Enable Signals and Start-up Time
  • 11.4 Watchdog Timer
    • 11.4.1 Features
    • 11.4.2 Overview
  • 11.5 Register Description
    • 11.5.1 MCUSR – MCU Status Register
    • 11.5.2 WDTCSR – Watchdog Timer Control Register
• 12. Interrupts
  • 12.1 Interrupt Vectors in ATmega16M1/32M1/64M1
    • 12.1.1 Moving Interrupts Between Application and Boot Space
  • 12.2 Register Description
    • 12.2.1 MCUCR – MCU Control Register
• 13. External Interrupts
  • 13.1 Pin Change Interrupt Timing
  • 13.2 Register Description
    • 13.2.1 EICRA – External Interrupt Control Register A
    • 13.2.2 EIMSK – External Interrupt Mask Register
    • 13.2.3 EIFR – External Interrupt Flag Register
    • 13.2.4 PCICR – Pin Change Interrupt Control Register
    • 13.2.5 PCIFR – Pin Change Interrupt Flag Register
    • 13.2.6 PCMSK3 – Pin Change Mask Register 3
    • 13.2.7 PCMSK2 – Pin Change Mask Register 2
    • 13.2.8 PCMSK1 – Pin Change Mask Register 1
    • 13.2.9 PCMSK0 – Pin Change Mask Register 0
• 14. I/O-Ports
  • 14.1 Overview
  • 14.2 Ports as General Digital I/O
    • 14.2.1 Configuring the Pin
    • 14.2.2 Toggling the Pin
    • 14.2.3 Switching Between Input and Output
    • 14.2.4 Reading the Pin Value
    • 14.2.5 Digital Input Enable and Sleep Modes
  • 14.3 Alternate Port Functions
    • 14.3.1 Alternate Functions of Port B
    • 14.3.2 Alternate Functions of Port C
    • 14.3.3 Alternate Functions of Port D
    • 14.3.4 Alternate Functions of Port E
  • 14.4 Register Description
    • 14.4.1 MCUCR – MCU Control Register
    • 14.4.2 PORTB – Port B Data Register
    • 14.4.3 DDRB – Port B Data Direction Register
    • 14.4.4 PINB – Port B Input Pins Address
    • 14.4.5 PORTC – Port C Data Register
    • 14.4.6 DDRC – Port C Data Direction Register
    • 14.4.7 PINC – Port C Input Pins Address
    • 14.4.8 PORTD – Port D Data Register
    • 14.4.9 DDRD – Port D Data Direction Register
    • 14.4.10 PIND – Port D Input Pins Address
    • 14.4.11 PORTE – Port E Data Register
    • 14.4.12 DDRE – Port E Data Direction Register
    • 14.4.13 PINE – Port E Input Pins Address
• 15. 8-bit Timer/Counter0 with PWM
  • 15.1 Features
  • 15.2 Overview
    • 15.2.1 Definitions
    • 15.2.2 Registers
  • 15.3 Timer/Counter Clock Sources
  • 15.4 Counter Unit
  • 15.5 Output Compare Unit
    • 15.5.1 Force Output Compare
    • 15.5.2 Compare Match Blocking by TCNT0 Write
    • 15.5.3 Using the Output Compare Unit
  • 15.6 Compare Match Output Unit
    • 15.6.1 Compare Output Mode and Waveform Generation
  • 15.7 Modes of Operation
    • 15.7.1 Normal Mode
    • 15.7.2 Clear Timer on Compare Match (CTC) Mode
    • 15.7.3 Fast PWM Mode
    • 15.7.4 Phase Correct PWM Mode
  • 15.8 Timer/Counter Timing Diagrams
  • 15.9 Register Description
    • 15.9.1 TCCR0A – Timer/Counter Control Register A
    • 15.9.2 TCCR0B – Timer/Counter Control Register B
    • 15.9.3 TCNT0 – Timer/Counter Register
    • 15.9.4 OCR0A – Output Compare Register A
    • 15.9.5 OCR0B – Output Compare Register B
    • 15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
    • 15.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• 16. 16-bit Timer/Counter1 with PWM
  • 16.1 Features
  • 16.2 Overview
    • 16.2.1 Registers
    • 16.2.2 Definitions
  • 16.3 Accessing 16-bit Registers
    • 16.3.1 Reusing the Temporary High Byte Register
  • 16.4 Timer/Counter Clock Sources
  • 16.5 Counter Unit
  • 16.6 Input Capture Unit
    • 16.6.1 Input Capture Trigger Source
    • 16.6.2 Noise Canceler
    • 16.6.3 Using the Input Capture Unit
    • 16.6.4 Using the Input Capture Unit as TCNT1 Retrigger Input
  • 16.7 Output Compare Units
    • 16.7.1 Force Output Compare
    • 16.7.2 Compare Match Blocking by TCNTn Write
    • 16.7.3 Using the Output Compare Unit
  • 16.8 Compare Match Output Unit
    • 16.8.1 Compare Output Mode and Waveform Generation
  • 16.9 Modes of Operation
    • 16.9.1 Normal Mode
    • 16.9.2 Clear Timer on Compare Match (CTC) Mode
    • 16.9.3 Fast PWM Mode
    • 16.9.4 Phase Correct PWM Mode
    • 16.9.5 Phase and Frequency Correct PWM Mode
  • 16.10 Timer/Counter Timing Diagrams
  • 16.11 Register Description
    • 16.11.1 TCCR1A – Timer/Counter1 Control Register A
    • 16.11.2 TCCR1B – Timer/Counter1 Control Register B
    • 16.11.3 TCCR1C – Timer/Counter1 Control Register C
    • 16.11.4 TCNT1H and TCNT1L – Timer/Counter1
    • 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
    • 16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
    • 16.11.7 ICR1H and ICR1L – Input Capture Register 1
    • 16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
    • 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
• 17. Timer/Counter0 and Timer/Counter1 Prescalers
  • 17.1 Internal Clock Source
  • 17.2 Prescaler Reset
  • 17.3 External Clock Source
  • 17.4 Register Description
    • 17.4.1 GTCCR – General Timer/Counter Control Register
• 18. PSC – Power Stage Controller
  • 18.1 Features
  • 18.2 Overview
  • 18.3 Accessing 16-bit Registers
  • 18.4 PSC Description
  • 18.5 Functional Description
    • 18.5.1 Generation of Control Waveforms
    • 18.5.2 Waveform Cycles
    • 18.5.3 Operation Mode Descriptions
      • 18.5.3.1 One Ramp Mode (Edge-Aligned)
      • 18.5.3.2 Center Aligned Mode
  • 18.6 Update of Values
    • 18.6.1 Value Update Synchronization
  • 18.7 Overlap Protection
  • 18.8 Signal Description
    • 18.8.1 Input Description
    • 18.8.2 Output Description
  • 18.9 PSC Input
    • 18.9.1 PSC Input Configuration
      • 18.9.1.1 Filter Enable
      • 18.9.1.2 Signal Polarity
      • 18.9.1.3 Input Mode Operation
  • 18.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing.
  • 18.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action
  • 18.12 Analog Synchronization
  • 18.13 Interrupt Handling
  • 18.14 PSC Clock Sources
  • 18.15 Interrupts
    • 18.15.1 Interrupt Vector
    • 18.15.2 PSC Interrupt Vectors in ATmega16M1/32M1/64M1
  • 18.16 Register Description
    • 18.16.1 POC – PSC Output Configuration
    • 18.16.2 PSYNC – PSC Synchro Configuration
    • 18.16.3 POCRnSAH and POCRnSAL – PSC Output Compare SA Register
    • 18.16.4 POCRnRAH and POCRnRAL – PSC Output Compare RA Register
    • 18.16.5 POCRnSBH and POCRnSBL – PSCOutput Compare SB Register
    • 18.16.6 POCRnRBH and POCRnRBL – PSC Output Compare RB Register
    • 18.16.7 PCNF – PSC Configuration Register
    • 18.16.8 PCTL – PSC Control Register
    • 18.16.9 PMICn – PSC Module n Input Control Register
    • 18.16.10 PSC Interrupt Mask Register – PIM
    • 18.16.11 PIFR – PSC Interrupt Flag Register
• 19. SPI – Serial Peripheral Interface
  • 19.1 Features
  • 19.2 Overview
  • 19.3 SS Pin Functionality
    • 19.3.1 Slave Mode
    • 19.3.2 Master Mode
  • 19.4 Data Modes
  • 19.5 Register Description
    • 19.5.1 MCUCR – MCU Control Register
    • 19.5.2 SPCR – SPI Control Register
    • 19.5.3 SPSR – SPI Status Register
    • 19.5.4 SPDR – SPI Data Register
• 20. CAN – Controller Area Network
  • 20.1 Features
  • 20.2 Overview
  • 20.3 CAN Protocol
    • 20.3.1 Principles
    • 20.3.2 Message Formats
      • 20.3.2.1 Can Standard Frame
      • 20.3.2.2 CAN Extended Frame
      • 20.3.2.3 Format Co-existence
    • 20.3.3 CAN Bit Timing
      • 20.3.3.1 Bit Construction
      • 20.3.3.2 Synchronization Segment
      • 20.3.3.3 Propagation Time Segment
      • 20.3.3.4 Phase Segment 1
      • 20.3.3.5 Sample Point
      • 20.3.3.6 Phase Segment 2
      • 20.3.3.7 Information Processing Time
      • 20.3.3.8 Bit Lengthening
      • 20.3.3.9 Bit Shortening
      • 20.3.3.10 Synchronization Jump Width
      • 20.3.3.11 Programming the Sample Point
      • 20.3.3.12 Synchronization
    • 20.3.4 Arbitration
    • 20.3.5 Errors
      • 20.3.5.1 Error at Message Level
      • 20.3.5.2 Error at Bit Level
      • 20.3.5.3 Error Signalling
  • 20.4 CAN Controller
  • 20.5 CAN Channel
    • 20.5.1 Configuration
    • 20.5.2 Bit Timing
    • 20.5.3 Baud Rate
    • 20.5.4 Fault Confinement
    • 20.5.5 Overload Frame
  • 20.6 Message Objects
    • 20.6.1 Number of MObs
    • 20.6.2 Operating Modes
      • 20.6.2.1 Disabled
      • 20.6.2.2 Tx Data & Remote Frame
      • 20.6.2.3 Rx Data & Remote Frame
      • 20.6.2.4 Automatic Reply
      • 20.6.2.5 Frame Buffer Receive Mode
    • 20.6.3 Acceptance Filter
    • 20.6.4 MOb Page
    • 20.6.5 CAN Data Buffers
  • 20.7 CAN Timer
    • 20.7.1 Prescaler
    • 20.7.2 16-bit Timer
    • 20.7.3 Time Triggering
    • 20.7.4 Stamping Message
  • 20.8 Error Management
    • 20.8.1 Fault Confinement
    • 20.8.2 Error Types
    • 20.8.3 Error Setting
  • 20.9 Interrupts
    • 20.9.1 Interrupt organization
    • 20.9.2 Interrupt Behavior
  • 20.10 Register Description
    • 20.10.1 CANGCON – CAN General Control Register
    • 20.10.2 CANGSTA – CAN General Status Register
    • 20.10.3 CANGIT – CAN General Interrupt Register
    • 20.10.4 CANGIE – CAN General Interrupt Enable Register
    • 20.10.5 CANEN2 and CANEN1 – CAN Enable MOb Registers
    • 20.10.6 CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers
    • 20.10.7 CANSIT2 and CANSIT1 – CAN Status Interrupt MOb Registers
    • 20.10.8 CANBT1 – CAN Bit Timing Register 1
    • 20.10.9 CANBT2 – CAN Bit Timing Register 2
    • 20.10.10 CANBT3 – CAN Bit Timing Register 3
    • 20.10.11 CANTCON – CAN Timer Control Register
    • 20.10.12 CANTIML and CANTIMH – CAN Timer Registers
    • 20.10.13 CANTTCL and CANTTCH – CAN TTC Timer Registers
    • 20.10.14 CANTEC – CAN Transmit Error Counter Register
    • 20.10.15 CANREC – CAN Receive Error Counter Register
    • 20.10.16 CANHPMOB – CAN Highest Priority MOb Register
    • 20.10.17 CANPAGE – CAN Page MOb Register
  • 20.11 MOb Registers
    • 20.11.1 CANSTMOB – CAN MOb Status Register
    • 20.11.2 CANCDMOB – CAN MOb Control and DLC Register
    • 20.11.3 CANIDT1, CANIDT2, CANIDT3, and CANIDT4 – CAN Identifier Tag Registers
    • 20.11.4 CANIDM1, CANIDM2, CANIDM3, and CANIDM4 – CAN Identifier Mask Registers
    • 20.11.5 CANSTML and CANSTMH – CAN Time Stamp Registers
    • 20.11.6 CANMSG – CAN Data Message Register
  • 20.12 Examples of CAN Baud Rate Setting
• 21. LIN / UART - Local Interconnect Network Controller or UART
  • 21.1 Features
    • 21.1.1 LIN
    • 21.1.2 UART
  • 21.2 Overview
  • 21.3 LIN Protocol
    • 21.3.1 Master and Slave
    • 21.3.2 Frames
    • 21.3.3 Data Transport
    • 21.3.4 Schedule Table
    • 21.3.5 Compatibility with LIN 1.3
  • 21.4 LIN / UART Controller
    • 21.4.1 LIN Overview
    • 21.4.2 UART Overview
    • 21.4.3 LIN/UART Controller Structure
    • 21.4.4 LIN/UART Command Overview
    • 21.4.5 Enable / Disable
    • 21.4.6 LIN Commands
      • 21.4.6.1 Rx Header / LIN Abort Function
      • 21.4.6.2 Tx Header Function
      • 21.4.6.3 Rx & TX Response Functions
      • 21.4.6.4 Handling Data of LIN response
    • 21.4.7 UART Commands
      • 21.4.7.1 Data Handling
      • 21.4.7.2 Rx Service
      • 21.4.7.3 Tx Service
  • 21.5 LIN / UART Description
    • 21.5.1 Reset
    • 21.5.2 Clock
    • 21.5.3 LIN Protocol Selection
    • 21.5.4 Configuration
    • 21.5.5 Busy Signal
      • 21.5.5.1 Busy Signal in LIN Mode
      • 21.5.5.2 Busy Signal in UART Mode
    • 21.5.6 Bit Timing
      • 21.5.6.1 Baud rate Generator
      • 21.5.6.2 Re-synchronization in LIN Mode
      • 21.5.6.3 Handling LBT[5:0]
    • 21.5.7 Data Length
      • 21.5.7.1 Data Length in LIN 2.1
      • 21.5.7.2 Data Length in LIN 1.3
      • 21.5.7.3 Data Length in Rx Response
      • 21.5.7.4 Data Length in Tx Response
      • 21.5.7.5 Data Length after Error
      • 21.5.7.6 Data Length in UART Mode
    • 21.5.8 xxOK Flags
    • 21.5.9 xxERR Flags
    • 21.5.10 Frame Time Out
    • 21.5.11 Break-in-data
    • 21.5.12 Checksum
    • 21.5.13 Interrupts
    • 21.5.14 Message Filtering
    • 21.5.15 Data Management
      • 21.5.15.1 LIN FIFO Data Buffer
      • 21.5.15.2 UART Data Register
    • 21.5.16 OCD Support
  • 21.6 Register Description
    • 21.6.1 LINCR – LIN Control Register
    • 21.6.2 LINSIR – LIN Status and Interrupt Register
    • 21.6.3 LINENIR – LIN Enable Interrupt Register
    • 21.6.4 LINERR – LIN Error Register
    • 21.6.5 LINBTR – LIN Bit Timing Register
    • 21.6.6 LINBRR – LIN Baud Rate Register
    • 21.6.7 LINDLR – LIN Data Length Register
    • 21.6.8 LINIDR – LIN Identifier Register
    • 21.6.9 LINSEL – LIN Data Buffer Selection Register
    • 21.6.10 LINDAT – LIN Data Register
• 22. ADC – Analog to Digital Converter
  • 22.1 Features
  • 22.2 Operation
  • 22.3 Starting a Conversion
  • 22.4 Prescaling and Conversion Timing
  • 22.5 Changing Channel or Reference Selection
    • 22.5.1 ADC Input Channels
    • 22.5.2 ADC Voltage Reference
  • 22.6 ADC Noise Canceler
    • 22.6.1 Analog Input Circuitry
    • 22.6.2 Analog Noise Canceling Techniques
    • 22.6.3 Offset Compensation Schemes
    • 22.6.4 ADC Accuracy Definitions
  • 22.7 ADC Conversion Result
  • 22.8 Temperature Measurement
    • 22.8.1 User Calibration
    • 22.8.2 Manufacturing Calibration
  • 22.9 Amplifier
  • 22.10 Register Description
    • 22.10.1 ADMUX – ADC Multiplexer Register
    • 22.10.2 Bit 4: 0 – MUX[4:0]: ADC Channel Selection Bits
    • 22.10.3 ADCSRA – ADC Control and Status Register A
    • 22.10.4 ADCSRB – ADC Control and Status Register B
    • 22.10.5 ADCH and ADCL – ADC Result Data Registers
      • 22.10.5.1 ADLAR = 0
      • 22.10.5.2 ADLAR = 1
    • 22.10.6 DIDR0 – Digital Input Disable Register 0
    • 22.10.7 DIDR1 – Digital Input Disable Register 1
    • 22.10.8 AMP0CSR – Amplifier 0 Control and Status register
    • 22.10.9 AMP1CSR – Amplifier 1 Control and Status register
    • 22.10.10 AMP2CSR – Amplifier 2 Control and Status register
• 23. ISRC - Current Source
  • 23.1 Features
  • 23.2 Typical applications
    • 23.2.1 LIN Current Source
    • 23.2.2 Voltage Reference for External Devices
    • 23.2.3 Threshold Reference for Internal Analog Comparator
  • 23.3 Register Description
    • 23.3.1 ADCSRB – ADC Control and Status Register B
• 24. AC – Analog Comparator
  • 24.1 Features
  • 24.2 Overview
  • 24.3 Use of ADC Amplifiers
  • 24.4 Register Description
    • 24.4.1 AC0CON – Analog Comparator 0 Control Register
    • 24.4.2 AC1CON – Analog Comparator 1Control Register
    • 24.4.3 AC2CON – Analog Comparator 2 Control Register
    • 24.4.4 AC3CON – Analog Comparator 3 Control Register
    • 24.4.5 ACSR – Analog Comparator Status Register
    • 24.4.6 DIDR0 – Digital Input Disable Register 0
    • 24.4.7 DIDR1 – Digital Input Disable Register 1
• 25. DAC – Digital to Analog Converter
  • 25.1 Features
  • 25.2 Overview
  • 25.3 Operation
  • 25.4 Starting a Conversion
    • 25.4.1 DAC Voltage Reference
  • 25.5 Register Description
    • 25.5.1 DACON – Digital to Analog Conversion Control Register
    • 25.5.2 DACH and DACL – Digital to Analog Converter input Register
      • 25.5.2.1 DALA = 0
      • 25.5.2.2 DALA = 1
• 26. debugWIRE On-chip Debug System
  • 26.1 Features
  • 26.2 Overview
  • 26.3 Physical Interface
  • 26.4 Software Break Points

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