Document Outline

• 1. Pin Descriptions
• 2. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • DAC Analog Characteristics
  • DAC Combined Interpolation & On-Chip Analog FIlter Response
    • Figure 1. DAC Output Test Load
    • Figure 2. Maximum DAC Loading
  • ADC Analog Characteristics
  • ADC Analog Characteristics
  • ADC Digital Filter Characteristics
  • Auxiliary Output Analog Characteristics
  • Auxiliary Output Analog Characteristics
  • Auxiliary Output Analog Characteristics
  • DC Electrical Characteristics
  • Digital Interface Characteristics
  • Switching Characteristics - Serial Audio Port 1
    • Figure 3. Master Mode Timing - Serial Audio Port 1
    • Figure 4. Slave Mode Timing - Serial Audio Port 1
  • Switching Characteristics - Serial Audio Port 2
    • Figure 5. Master Mode Timing - Serial Audio Port 2
    • Figure 6. Slave Mode Timing - Serial Audio Port 2
    • Figure 7. Format 0, Left-Justified up to 24-Bit Data
    • Figure 8. Format 1, I·S up to 24-Bit Data
    • Figure 9. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data.
  • Switching Characteristics - Control Port - I·C Format
    • Figure 10. Control Port Timing - I·C Format
  • Switching Characteristics - Control Port - SPI Format
    • Figure 11. Control Port Timing - SPI Format
• 3. Typical Connection Diagram
  • Figure 12. Typical Connection Diagram
• 4. Applications
  • 4.1 Recommended Power-Up Sequence
  • 4.2 System Clocking
    • Table 1. Speed Modes
    • 4.2.1 Synchronous / Asynchronous Mode
    • 4.2.2 Master Clock
      • Table 2. Common Clock Frequencies
      • Table 3. MCLK Dividers
    • 4.2.3 Master Mode
      • Figure 13. Master Mode Clocking
    • 4.2.4 Slave Mode
      • Table 4. Slave Mode Serial Bit Clock Ratios
  • 4.3 High-Pass Filter and DC Offset Calibration
  • 4.4 Analog Input Multiplexer, PGA, and Mic Gain
    • Figure 14. Analog Input Architecture
  • 4.5 Input Connections
  • 4.6 Output Connections
  • 4.7 Output Transient Control
    • 4.7.1 Power-Up
    • 4.7.2 Power-Down
    • 4.7.3 Serial Interface Clock Changes
  • 4.8 Auxiliary Analog Output
  • 4.9 De-Emphasis Filter
    • Figure 15. De-Emphasis Curve
  • 4.10 Internal Digital Loopback
  • 4.11 Mute Control
    • Figure 16. Suggested Active-Low Mute Circuit
  • 4.12 Control Port Description and Timing
    • 4.12.1 SPI Mode
      • Figure 17. Control Port Timing in SPI Mode
    • 4.12.2 I·C Mode
      • Figure 18. Control Port Timing, I·C Write
      • Figure 19. Control Port Timing, I·C Read
  • 4.13 Interrupts and Overflow
  • 4.14 Reset
  • 4.15 Synchronization of Multiple Devices
  • 4.16 Grounding and Power Supply Decoupling
• 5. Register Quick Reference
• 6. Register Description
  • 6.1 Chip ID - Register 01h
    • Table 5. Device Revision
  • 6.2 Power Control - Address 02h
    • 6.2.1 Freeze (Bit 7)
      • Table 6. Freeze-able Bits
    • 6.2.2 Power-Down MIC (Bit 3)
    • 6.2.3 Power-Down ADC (Bit 2)
    • 6.2.4 Power-Down DAC (Bit 1)
    • 6.2.5 Power-Down Device (Bit 0)
  • 6.3 DAC Control - Address 03h
    • 6.3.1 DAC Functional Mode (Bits 7:6)
      • Table 7. Functional Mode Selection
    • 6.3.2 DAC Digital Interface Format (Bits 5:4)
      • Table 8. DAC Digital Interface Formats
    • 6.3.3 Mute DAC (Bit 2)
    • 6.3.4 De-Emphasis Control (Bit 1)
      • Table 9. De-Emphasis Control
      • Figure 20. De-Emphasis Curve
    • 6.3.5 DAC Master / Slave Mode (Bit 0)
  • 6.4 ADC Control - Address 04h
    • 6.4.1 ADC Functional Mode (Bits 7:6)
      • Table 10. Functional Mode Selection
    • 6.4.2 ADC Digital Interface Format (Bit 4)
      • Table 11. ADC Digital Interface Formats
    • 6.4.3 Mute ADC (Bit 2)
    • 6.4.4 ADC High-Pass Filter Freeze (Bit 1)
    • 6.4.5 ADC Master / Slave Mode (Bit 0)
  • 6.5 MCLK Frequency - Address 05h
    • 6.5.1 Master Clock 1 Frequency (Bits 6:4)
      • Table 12. MCLK 1 Frequency
    • 6.5.2 Master Clock 2 Frequency (Bits 2:0)
      • Table 13. MCLK 2 Frequency
  • 6.6 Signal Selection - Address 06h
    • 6.6.1 Auxiliary Output Source Select (Bits 6:5)
      • Table 14. Auxiliary Output Source Selection
    • 6.6.2 Digital Loopback (Bit 1)
    • 6.6.3 Asynchronous Mode (Bit 0)
  • 6.7 Channel B PGA Control - Address 07h
    • 6.7.1 Channel B PGA Gain (Bits 5:0)
  • 6.8 Channel A PGA Control - Address 08h
    • 6.8.1 Channel A PGA Gain (Bits 5:0)
      • Table 15. Example Gain and Attenuation Settings
  • 6.9 ADC Input Control - Address 09h
    • 6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
      • Table 16. PGA Soft Cross or Zero Cross Mode Selection
    • 6.9.2 Analog Input Selection (Bits 2:0)
      • Table 17. Analog Input Multiplexer Selection
  • 6.10 DAC Channel A Volume Control - Address 0Ah
  • 6.11 DAC Channel B Volume Control - Address 0Bh
    • 6.11.1 Volume Control (Bits 7:0)
      • Table 18. Digital Volume Control Example Settings
  • 6.12 DAC Control 2 - Address 0Ch
    • 6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
      • Table 19. DAC Soft Cross or Zero Cross Mode Selection
    • 6.12.2 Invert DAC Output (Bit 5)
    • 6.12.3 Active High/Low (Bit 0)
  • 6.13 Interrupt Status - Address 0Dh
    • 6.13.1 ADC Clock Error (Bit 3)
    • 6.13.2 DAC Clock Error (Bit 2)
    • 6.13.3 ADC Overflow (Bit 1)
    • 6.13.4 ADC Underflow (Bit 0)
  • 6.14 Interrupt Mask - Address 0Eh
  • 6.15 Interrupt Mode MSB - Address 0Fh
  • 6.16 Interrupt Mode LSB - Address 10h
• 7. Parameter Definitions
• 8. DAC Filter Plots
  • Figure 21. DAC Single-Speed Stopband Rejection
  • Figure 22. DAC Single-Speed Transition Band
  • Figure 23. DAC Single-Speed Transition Band
  • Figure 24. DAC Single-Speed Passband Ripple
  • Figure 25. DAC Double-Speed Stopband Rejection
  • Figure 26. DAC Double-Speed Transition Band
  • Figure 27. DAC Double-Speed Transition Band
  • Figure 28. DAC Double-Speed Passband Ripple
  • Figure 29. DAC Quad-Speed Stopband Rejection
  • Figure 30. DAC Quad-Speed Transition Band
  • Figure 31. DAC Quad-Speed Transition Band
  • Figure 32. DAC Quad-Speed Passband Ripple
• 9. ADC Filter Plots
  • Figure 33. ADC Single-Speed Stopband Rejection
  • Figure 34. ADC Single-Speed Stopband Rejection
  • Figure 35. ADC Single-Speed Transition Band (Detail)
  • Figure 36. ADC Single-Speed Passband Ripple
  • Figure 37. ADC Double-Speed Stopband Rejection
  • Figure 38. ADC Double-Speed Stopband Rejection
  • Figure 39. ADC Double-Speed Transition Band (Detail)
  • Figure 40. ADC Double-Speed Passband Ripple
  • Figure 41. ADC Quad-Speed Stopband Rejection
  • Figure 42. ADC Quad-Speed Stopband Rejection
  • Figure 43. ADC Quad-Speed Transition Band (Detail)
  • Figure 44. ADC Quad-Speed Passband Ripple
• 10. Package Dimensions
• 11. Thermal Characteristics and Specifications
• 12. Ordering Information
• 13. Revision History