Document Outline

• Major Revisions in This Edition
• INTRODUCTION
• CHAPTER 1 GENERAL
  • 1.1 Features
  • 1.2 Applications
  • 1.3 Ordering Information
  • 1.4 Pin Configuration (Top View)
  • 1.5 78K/0S Series Lineup
  • 1.6 Block Diagram
  • 1.7 Functions
• CHAPTER 2 PIN FUNCTIONS
  • 2.1 List of Pin Functions
  • 2.2 Pin Functions
    • 2.2.1 P00 to P07 (Port 0)
    • 2.2.2 P10 to P17 (Port 1)
    • 2.2.3 P20 to P26 (Port 2)
    • 2.2.4 P40 to P47 (Port 4)
    • 2.2.5 RESET#
    • 2.2.6 X1, X2
    • 2.2.7 REGC
    • 2.2.8 USBDM
    • 2.2.9 USBDP
    • 2.2.10 VDD0, VDD1
    • 2.2.11 VSS0, VSS1
    • 2.2.12 VPP (uPD78F9801 only)
    • 2.2.13 IC (mask ROM version only)
  • 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
• CHAPTER 3 CPU ARCHITECTURE
  • 3.1 Memory Space
    • 3.1.1 Internal program memory space
    • 3.1.2 Internal data memory (internal high-speed RAM) space
    • 3.1.3 Special function register (SFR) area
    • 3.1.4 Data memory addressing
  • 3.2 Processor Registers
    • 3.2.1 Control registers
    • 3.2.2 General-purpose registers
    • 3.2.3 Special function registers (SFRs)
  • 3.3 Instruction Address Addressing
    • 3.3.1 Relative addressing
    • 3.3.2 Immediate addressing
    • 3.3.3 Table indirect addressing
    • 3.3.4 Register addressing
  • 3.4 Operand Address Addressing
    • 3.4.1 Direct addressing
    • 3.4.2 Short direct addressing
    • 3.4.3 Special function register (SFR) addressing
    • 3.4.4 Register addressing
    • 3.4.5 Register indirect addressing
    • 3.4.6 Based addressing
    • 3.4.7 Stack addressing
• CHAPTER 4 PORT FUNCTIONS
  • 4.1 Port Functions
  • 4.2 Port Configuration
    • 4.2.1 Port 0
    • 4.2.2 Port 1
    • 4.2.3 Port 2
    • 4.2.4 Port 4
  • 4.3 Registers Controlling Port Function
  • 4.4 Port Function Operation
    • 4.4.1 Writing to I/O port
    • 4.4.2 Reading from I/O port
    • 4.4.3 Arithmetic operation of I/O port
• CHAPTER 5 CLOCK GENERATOR
  • 5.1 Clock Generator Functions
  • 5.2 Clock Generator Configuration
  • 5.3 Register Controlling Clock Generator
  • 5.4 System Clock Oscillators
    • 5.4.1 System clock oscillator
    • 5.4.2 Examples of incorrect resonator connection
    • 5.4.3 Frequency divider
  • 5.5 Clock Generator Operation
  • 5.6 Changing Setting of CPU Clock
    • 5.6.1 Time required for switching CPU clock
    • 5.6.2 Switching CPU clock
• CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01
  • 6.1 Functions of 8-Bit Timer/Event Counters 00 and 01
  • 6.2 Configuration of 8-Bit Timer/Event Counters 00 and 01
  • 6.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01
  • 6.4 Operation of 8-Bit Timer/Event Counters 00 and 01
    • 6.4.1 Operation as interval timer
    • 6.4.2 Operation as external event counter (timer 01 only)
    • 6.4.3 Operation as square-wave output (timer 01 only)
  • 6.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01
• CHAPTER 7 WATCHDOG TIMER
  • 7.1 Watchdog Timer Functions
  • 7.2 Watchdog Timer Configuration
  • 7.3 Registers Controlling Watchdog Timer
  • 7.4 Watchdog Timer Operation
    • 7.4.1 Operation as watchdog timer
    • 7.4.2 Operation as interval timer
• CHAPTER 8 USB FUNCTION
  • 8.1 USB Overview
  • 8.2 USB Function Features
  • 8.3 USB Function Configuration
  • 8.4 Registers Controlling USB Function
  • 8.5 USB Function Operation
    • 8.5.1 USB timer operation
    • 8.5.2 Remote wakeup control operation
  • 8.6 Interrupt Request from USB Function
    • 8.6.1 Interrupt sources
    • 8.6.2 Cautions when using interrupts
  • 8.7 USB Function Control
    • 8.7.1 Relationship between packets and operation modes
    • 8.7.2 Interrupt servicing flow
  • 8.8 USB Function Internal Circuit Operations
    • 8.8.1 Operation of transmit/receive pointer
    • 8.8.2 Receive bank switching ID detection buffer operation
    • 8.8.3 Sync detection/USBCLK detector operation
    • 8.8.4 NRZI encoder operation
    • 8.8.5 Bit stuffing/strip controller operation
• CHAPTER 9 SERIAL INTERFACE 10
  • 9.1 Functions of Serial Interface 10
  • 9.2 Configuration of Serial Interface 10
  • 9.3 Register Controlling Serial Interface 10
  • 9.4 Operation of Serial Interface 10
    • 9.4.1 Operation stop mode
    • 9.4.2 3-wire serial I/O mode
• CHAPTER 10 REGULATOR
• CHAPTER 11 INTERRUPT FUNCTIONS
  • 11.1 Interrupt Function Types
  • 11.2 Interrupt Sources and Configuration
  • 11.3 Registers Controlling Interrupt Function
  • 11.4 Interrupt Servicing Operation
    • 11.4.1 Non-maskable interrupt acknowledgment operation
    • 11.4.2 Maskable interrupt acknowledgment operation
    • 11.4.3 Multiplexed interrupt servicing
    • 11.4.4 Interrupt request hold
• CHAPTER 12 STANDBY FUNCTION
  • 12.1 Standby Function and Configuration
    • 12.1.1 Standby function
    • 12.1.2 Register controlling standby function
  • 12.2 Standby Function Operation
    • 12.2.1 HALT mode
    • 12.2.2 STOP mode
• CHAPTER 13 RESET FUNCTION
• CHAPTER 14 uPD78F9801
  • 14.1 Flash Memory Characteristics
    • 14.1.1 Programming environment
    • 14.1.2 Communication mode
    • 14.1.3 On-board pin processing
    • 14.1.4 Connection of adapter for flash writing
• CHAPTER 15 INSTRUCTION SET
  • 15.1 Operation
    • 15.1.1 Operand identifiers and description methods
    • 15.1.2 Description of “operation” column
    • 15.1.3 Description of “flag operation” column
  • 15.2 Operation List
  • 15.3 Instructions Listed by Addressing Type
• CHAPTER 16 ELECTRICAL SPECIFICATIONS
• CHAPTER 17 PACKAGE DRAWINGS
• CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS
  • A.1 Software Package
  • A.2 Language Processing Software
  • A.3 Control Software
  • A.4 Flash Memory Writing Tools
  • A.5 Debugging Tools (Hardware)
  • A.6 Debugging Tools (Software)
  • A.7 Notes on Target System Design
• APPENDIX A DEVELOPMENT TOOLS
• APPENDIX B REGISTER INDEX
  • B.1 Register Index (Alphabetic Order of Register Name)
  • B.2 Register Index (Alphabetic Order of Register Symbol)
• APPENDIX C REVISION HISTORY