Document Outline

• Revision History
• Table of Contents
• Manual Objectives
  • About This Manual
  • Intended Audience
  • Manual Organization
    • Architectural Overview
    • Z8® Compatibility
    • Address Space
    • Addressing Modes
    • Interrupts
    • Illegal Instruction Traps
    • eZ8™ CPU Instruction Set Summary
    • Op Code Maps
    • Op Codes Listed Numerically
    • Sample Program Listing
  • Manual Conventions
    • Courier Typeface
    • Hexadecimal Values
    • Brackets
    • Braces
    • Parentheses
    • Parentheses/Bracket Combinations
    • Use of the Words Set, Reset, and Clear
    • Notation for Bits and Similar Registers
    • Use of the Terms LSB, MSB, lsb, and msb
    • Use of Initial Uppercase Letters
    • Bit Numbering
  • Safeguards
    • Abbreviations/Acronyms
• Architectural Overview
  • Processor Description
    • Fetch Unit
    • Execution Unit
  • eZ8™ CPU Control Registers
    • Stack Pointer Registers
    • Register Pointer
    • Flags Register
    • Condition Codes
    • Arithmetic Logic Unit
    • Byte Ordering
• Z8® Compatibility
  • Assembly Language Compatibility
  • New Instructions
    • New Function Instructions
    • Extended Addressing Instructions
    • Alternate Function Op Code
    • Moved Instructions
    • Removed Instructions
  • Relocation of eZ8 CPU Control Registers
    • Stack Pointer High and Low Byte Registers
    • Register Pointer
    • Flags Register
  • Compatibility with Z8 CPU
    • Stack Pointer Compatibility
    • Reset Compatibility
    • Interrupt Compatibility
• Address Space
  • Register File
    • CPU Control Registers
    • General-Purpose Registers
    • Register File Organization
    • Register File Precautions
  • Program Memory
  • Data Memory
  • Stacks
• Interrupts
  • Interrupt Enable and Disable
  • Interrupt Priority
  • Vectored Interrupt Processing
  • Nesting of Vectored Interrupts
  • Polled Interrupt Processing
  • Software Interrupt Generation
• Addressing Modes
  • Register Addressing
    • Register Addressing Using 12-Bit Addresses
    • Register Addressing Using 8-Bit Addresses
    • Register Addressing Using 4-Bit Addresses
    • Escaped Mode Addressing
  • Indirect Register Addressing
  • Indexed Addressing
  • Direct Addressing
  • Relative Addressing
  • Immediate Data Addressing
• Illegal Instruction Traps
  • Symbolic Operation of an Illegal Instruction Trap
    • Linear Programs That Do Not Employ The Stack
• eZ8™ CPU Instruction Set Summary
  • Assembly Language Source Program Example
  • Assembly Language Syntax
  • eZ8 CPU Instruction Notation
  • eZ8 CPU Instruction Classes
  • eZ8 CPU Instruction Summary
• eZ8™ CPU Instruction Set Description
  • ADC
  • ADCX
  • ADD
  • ADDX
  • AND
  • ANDX
  • ATM
  • BCLR
  • BIT
  • BRK
  • BSET
  • BSWAP
  • BTJ
  • BTJNZ
  • BTJZ
  • CALL
  • CCF
  • CLR
  • COM
  • CP
  • CPC
  • CPCX
  • CPX
  • DA
  • DEC
  • DECW
  • DI
  • DJNZ
  • EI
  • HALT
  • INC
  • INCW
  • IRET
  • JP
  • JP cc
  • JR
  • JR cc
  • LD
  • LDC
  • LDCI
  • LDE
  • LDEI
  • LDWX
  • LDX
  • LEA
  • MULT
  • NOP
  • OR
  • ORX
  • POP
  • POPX
  • PUSH
  • PUSHX
  • RCF
  • RET
  • RL
  • RLC
  • RR
  • RRC
  • SBC
  • SBCX
  • SCF
  • SRA
  • SRL
  • SRP
  • STOP
  • SUB
  • SUBX
  • SWAP
  • TCM
  • TCMX
  • TM
  • TMX
  • TRAP
  • WDT
  • XOR
  • XORX
• Op Code Maps
• Op Codes Listed Numerically
• Assembly and Object Code Example
• Index
• Customer Support