Document Outline

• ChapterTitlePreface - Preface
  • Heading1 - Introduction
  • Heading1 - Cell Naming Conventions
    • Heading2 - Register Naming Conventions
    • Heading2 - I/O Cell Naming Conventions
  • Heading1 - Conventions Used in this Guide
• ChapterTitle - Chapter 1 – I/O Cells
  • Table - Table 1-1: Supported Single-Ended Voltage Standards
  • Table - Table 1-2: Supported Differential Voltage Standards
  • Heading1 - IOPAD
    • Heading2 - Bidirectional I/O Pad
      • Figure - Figure 1-1: IOPAD Logic Symbol
      • Table - Table 1-3: Ports
      • Table - Table 1-4: Parameters
      • Table - Table 1-5: Output Function Table
      • Table - Table 1-6: Input Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IOPAD_D
    • Heading2 - Bidirectional Registered I/O Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-2: IOPAD_D Logic Symbol
      • Table - Table 1-7: Ports
      • Table - Table 1-8: Parameters
      • Table - Table 1-9: Output Function Table (txregmode = ”reg”, oeregmode = “reg”, rstmode = “async”)
      • Table - Table 1-10: Output Function Table (txregmode = ”reg”, oeregmode = “reg”, rstmode = “sync”)
      • Table - Table 1-11: Input Function table (rxregmode = “reg”)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IOPAD_D2
    • Heading2 - Bidirectional DDR I/O Pad with Asynchronous or Synchronous Set/ Reset
      • Figure - Figure 1-3: IOPAD_D2 Logic Symbol
      • Table - Table 1-12: Ports
      • Table - Table 1-13: Parameters
      • Figure - Figure 1-4: IOPAD_D2 Output Timing Diagram (assumes txdata_en = 1’b1)
      • Figure - Figure 1-5: IOPAD_D2 Input Timing Diagram (assumes rxdata_en = 1’b1)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IPAD
    • Heading2 - Non-Registered Input Pad
      • Figure - Figure 1-6: IPAD Logic Symbol
      • Table - Table 1-14: Ports
      • Table - Table 1-15: Parameters
      • Table - Table 1-16: Input Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IPAD_D
    • Heading2 - Registered Input Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-7: IPAD_D Logic Symbol
      • Table - Table 1-17: Ports
      • Table - Table 1-18: Parameters
      • Table - Table 1-19: Input Function table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IPAD_D2
    • Heading2 - DDR Input Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-8: IPAD_D2 Logic Symbol
      • Table - Table 1-20: Ports
      • Table - Table 1-21: Parameters
      • Figure - Figure 1-9: IPAD_D2 Input Timing Diagram (assumes data_en = 1’b1)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IPAD_DIFF
    • Heading2 - Non-Registered Differential Input Pad
      • Figure - Figure 1-10: IPAD_DIFF Logic Symbol
      • Table - Table 1-22: Ports
      • Table - Table 1-23: Parameters
      • Table - Table 1-24: Input Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IPAD_DIFFD
    • Heading2 - Registered Differential Input Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-11: IPAD_DIFFD Logic Symbol
      • Table - Table 1-25: Ports
      • Table - Table 1-26: Parameters
      • Table - Table 1-27: Input Function table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - IPAD_DIFFD2
    • Heading2 - DDR Differential Input Pad with Asynchronous or Synchronous Set/ Reset
      • Figure - Figure 1-12: IPAD_DIFFD2 Logic Symbol
      • Table - Table 1-28: Ports
      • Table - Table 1-29: Parameters
      • Figure - Figure 1-13: IPAD_DIFFD2 Input Timing Diagram (assumes data_en = 1’b1)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - OPAD
    • Heading2 - Non-Registered Output Pad
      • Figure - Figure 1-14: OPAD Logic Symbol
      • Table - Table 1-30: Ports
      • Table - Table 1-31: Parameters
      • Table - Table 1-32: Output Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - OPAD_D
    • Heading2 - Registered Output Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-15: OPAD_D Logic Symbol
      • Table - Table 1-33: Ports
      • Table - Table 1-34: Parameters
      • Table - Table 1-35: Output Function Table (rstmode = “async”)
      • Table - Table 1-36: Output Function Table (rstmode = “sync”)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - OPAD_D2
    • Heading2 - DDR Output Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-16: OPAD_D2 Logic Symbol
      • Table - Table 1-37: Ports
      • Table - Table 1-38: Parameters
      • Figure - Figure 1-17: OPAD_D2 Output Timing Diagram (assumes data_en = 1’b1)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - OPAD_DIFF
    • Heading2 - Non-Registered Differential Output Pad
      • Figure - Figure 1-18: OPAD_DIFF Logic Symbol
      • Table - Table 1-39: Ports
      • Table - Table 1-40: Parameters
      • Table - Table 1-41: Output Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - OPAD_DIFFD
    • Heading2 - Registered Differential Output Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-19: OPAD_DIFFD Logic Symbol
      • Table - Table 1-42: Ports
      • Table - Table 1-43: Parameters
      • Table - Table 1-44: Output Function Table (rstmode = “async”)
      • Table - Table 1-45: Output Function Table (rstmode = “sync”)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - OPAD_DIFFD2
    • Heading2 - DDR Differenctial Output Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-20: OPAD_DIFFD2 Logic Symbol
      • Table - Table 1-46: Ports
      • Table - Table 1-47: Parameters
      • Figure - Figure 1-21: OPAD_DIFFD2 Output Timing Diagram (assumes data_en = 1’b1)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - TPAD
    • Heading2 - Non-Registered Tristate Output Pad
      • Figure - Figure 1-22: TPAD Logic Symbol
      • Table - Table 1-48: Ports
      • Table - Table 1-49: Parameters
      • Table - Table 1-50: Output Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - TPAD_D
    • Heading2 - Registered Tristate Output Pad with Asynchronous or Synchronous Set/Reset
      • Figure - Figure 1-23: TPAD_D Logic Symbol
      • Table - Table 1-51: Ports
      • Table - Table 1-52: Parameters
      • Table - Table 1-53: Output Function Table (rstmode = “async”)
      • Table - Table 1-54: Output Function Table (rstmode = “sync”)
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
• ChapterTitle - Chapter 2 – Registers
  • Heading1 - Naming Convention
  • Heading1 - DFF
    • Heading2 - Positive Clock Edge D-Type Register
      • Figure - Figure 2-1: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-1: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-2: Parameters
      • Heading3 - init
      • Table - Table 2-3: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFE
    • Heading2 - Positive Clock Edge D-Type Register with Clock Enable
      • Figure - Figure 2-2: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-4: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-5: Parameters
      • Heading3 - init
      • Table - Table 2-6: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFEC
    • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Synchronous Clear
      • Figure - Figure 2-3: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-7: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-8: Parameters
      • Heading3 - init
      • Table - Table 2-9: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFEP
    • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Synchronous Preset
      • Figure - Figure 2-4: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-10: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-11: Parameters
      • Heading3 - init
      • Table - Table 2-12: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFER
    • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Reset
      • Figure - Figure 2-5: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-13: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-14: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-15: DFFER Function Table when sr_assertion = “unclocked”
      • Table - Table 2-16: DFFER Function Table when sr_assertion = “clocked”
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFES
    • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Set
      • Figure - Figure 2-6: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-17: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-18: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-19: DFFES Function Table when sr_assertion = “unclocked”
      • Table - Table 2-20: DFFES Function Table when sr_assertion = “clocked”
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFN
    • Heading2 - Negative Clock Edge D-Type Register
      • Figure - Figure 2-7: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-21: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-22: Parameters
      • Heading3 - init
      • Table - Table 2-23: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFNEC
    • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Synchronous Clear
      • Figure - Figure 2-8: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-24: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-25: Parameters
      • Heading3 - init
      • Table - Table 2-26: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFNEP
    • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Synchronous Preset
      • Figure - Figure 2-9: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-27: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-28: Parameters
      • Heading3 - init
      • Table - Table 2-29: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFNER
    • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Reset
      • Figure - Figure 2-10: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-30: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-31: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-32: DFFNER Function Table when sr_assertion = “unclocked”
      • Table - Table 2-33: DFFNER Function Table when sr_assertion = “clocked”
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFNES
    • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Set
      • Figure - Figure 2-11: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-34: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-35: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-36: DFFNES Function Table when sr_assertion = “unclocked”
      • Table - Table 2-37: DFFNES Function Table when sr_assertion = “clocked”
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFNR
    • Heading2 - Negative Clock Edge D-Type Register with Asynchronous Reset
      • Figure - Figure 2-12: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-38: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-39: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-40: Function Table when sr_assertion = “unclocked’
      • Table - Table 2-41: Function Table when sr_assertion = “clocked’
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFNS
    • Heading2 - Negative Clock Edge D-Type Register with Asynchronous Set
      • Figure - Figure 2-13: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-42: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-43: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-44: Function Table when sr_assertion = “unclocked’
      • Table - Table 2-45: unction Table when sr_assertion = “clocked’
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFR
    • Heading2 - Positive Clock Edge D-Type Register with Asynchronous Reset
      • Figure - Figure 2-14: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-46: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-47: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-48: Function Table when sr_assertion = “unclocked’
      • Table - Table 2-49: Function Table when sr_assertion = “clocked’
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
  • Heading1 - DFFS
    • Heading2 - Positive Clock Edge D-Type Register with Asynchronous Set
      • Figure - Figure 2-15: Logic Symbol
    • Heading2 - Pins
      • Table - Table 2-50: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 2-51: Parameters
      • Heading3 - init
      • Heading3 - sr_assertion
      • Table - Table 2-52: Function Table when sr_assertion = “unclocked’
      • Table - Table 2-53: Function Table when sr_assertion = “clocked’
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
• ChapterTitle - Chapter 3 – Logic Functions
  • Heading1 - MUX2
    • Heading2 - Two Input Multiplexer Gate
      • Figure - Figure 3-1: Logic Symbol
    • Heading2 - Pins
      • Table - Table 3-1: Pin Descriptions
      • Table - Table 3-2: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
• ChapterTitle - Chapter 4 – Lookup Table (LUT) Functions
  • Heading1 - LUT4
    • Heading2 - Four Input Lookup Table
      • Figure - Figure 4-1: Logic Symbol
    • Heading2 - Pins
      • Table - Table 4-1: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 4-2: Parameters
      • Heading3 - lut_function
      • Table - Table 4-3: Function Table
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
• ChapterTitle - Chapter 5 – Arithmetic Functions
  • Heading1 - ALU
    • Heading2 - Two Input Adder / Subtractor with Programmable Load
      • Figure - Figure 5-1: Logic Symbol
    • Heading2 - Pins
      • Table - Table 5-1: Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 5-2: Parameters
      • Heading3 - invert_b
      • Table - Table 5-3: Function Table When invert_b = 1’b0.
      • Table - Table 5-4: Function Table When invert_b = 1’b1.
      • Heading3 - Verilog Instantiation Template
      • Heading3 - VHDL Instantiation Template
• ChapterTitle - Chapter 6 – Memories
  • Heading1 - BRAM80K
    • Heading2 - 80k-bit Dual-Port Memory
      • Figure - Figure 6-1: Logic Symbol
      • Figure - Figure 6-2: BRAM80K Block Diagram (Per Port)
    • Heading2 - BRAM80K Pins
      • Table - Table 6-1: BRAM80K Pin Descriptions
    • Heading2 - Parameters
      • Table - Table 6-2: BRAM80K Parameters
      • Heading3 - porta_read_width(portb_read_width)
      • Heading3 - porta_write_width(portb_write_width)
      • Heading3 - porta_write_mode(portb_write_mode)
      • Heading3 - porta_clock_polarity(portb_clock_polarity)
      • Heading3 - porta_peval(portb_peval)
      • Heading3 - porta_latch_rstval(portb_latch_rstval)
      • Heading3 - porta_en_out_reg(portb_en_out_reg)
      • Heading3 - porta_reg_rstval(portb_reg_rstval)
      • Heading3 - porta_regce_priority(portb_regce_priority)
      • Heading3 - porta_initval(portb_initval)
      • Table - Table 6-3: Relationship of porta_initval(portb_initval) bit positions to douta,doutpa,doutpxa (doutb,doutpb,doutpxb)
      • Heading3 - porta_srval(portb_srval)
      • Table - Table 6-4: Relationship of porta_srval(portb_srval) bit positions to douta,doutpa,doutpxa (doutb,doutpb,doutpxb)
      • Heading3 - mem_init_file
      • Heading3 - initd_000 – initd_255
      • Heading3 - initp_00 – initp_31
      • Heading3 - initpx_00 – initpx_31
    • Heading2 - Memory Organization and Data Input / Output Pin Assignments
      • Table - Table 6-5: Valid Port A Width Versus Port B Width Combinations per port for n x 5 width modes
      • Table - Table 6-6: Valid Port A Width Versus Port B Width Combinations per port for n x 9 width modes
      • Table - Table 6-7: Valid Port A Width Versus Write Port B Combinations per port for n x 2 width modes
      • Table - Table 6-8: dina(dinb) bit assignments per porta_write_width(portb_write_width) values
      • Table - Table 6-9: Write Enable to Data Input Bus Mapping per Write Port Width
      • Table - Table 6-10: douta(doutb) bit assignments per porta_read_width(portb_read_width) values
      • Table - Table 6-11: BRAM80K Address Bus Mapping (Per Port)
      • Table - Table 6-12: Mapping of Word Sizes to the Native 2048x40 Memory Locations
    • Heading2 - Read and Write Operations
      • Heading3 - Read Operation
      • Heading3 - Write Operation
      • Table - Table 6-13: BRAM Output Function Table for Latched Mode (Assumes active-high clock, port enable, and latch reset value)
      • Table - Table 6-14: BRAM Output Function Table for Registered Mode (Assumes active-high clock, output register clock enable, and output register reset)
      • Heading3 - Simultaneous Memory Operations
      • Heading3 - Timing Diagrams
      • Figure - Figure 6-3: Write-First, Latched Mode Timing Diagram
      • Figure - Figure 6-4: Write-First, Registered Mode Timing Diagram
      • Figure - Figure 6-5: No-Change, Latched Mode Timing Diagram
      • Figure - Figure 6-6: No-Change, Registered Mode Timing Diagram
      • Heading3 - Support for Read-First (Read-Before-Write) Memory Operations
    • Heading2 - Memory Initialization
    • Heading2 - BRAM80K Verilog Instantiation Template
    • Heading2 - BRAM80K VHDL Instantiation Template
  • Heading1 - BRAM80KFIFO
    • Heading2 - 80k-bit FIFO Memory
      • Figure - Figure 6-7: Logic Symbol
      • Figure - Figure 6-8: BRAM80KFIFO Block Diagram
      • Table - Table 6-15: BRAM80KFIFO Pin Description
    • Heading2 - Parameters
      • Table - Table 6-16: BRAM80KFIFO Parameters
      • Heading3 - sync_mode
      • Heading3 - write_width
      • Table - Table 6-17: FIFO write_width versus Maximum Write Depth
      • Table - Table 6-18: din, dinp, dinpx bit assignments per write_width values
      • Heading3 - read_width
      • Table - Table 6-19: FIFO read_width versus Maximum Read Depth
      • Table - Table 6-20: dout bit assignme