DLS-75 Guide
User manual for DLS-75
Table of contents App Note - Interfacing Z80 CPUs to Z8500 App Note - Z180 Interfaced with SCC at MHZ App Note - Zilog Datacom Family with 80186 CPU App Note - SCC in Binary Syn Communications App Note - Serial Communications Controller SDLC Mode of Operation App Note - Using SCC with Z8000 in SDLC Protocol App Note - Boost Your System Performance Using Zilog ESCC App Note - Technical Considerations When Implementing LocalTalk Link Access Protocol App Note - On-Chip Oscillator Design App Note - Interfacing the ISCC to the 68000 and 8086 ISCC Controller - Questions and Answers
Document Outline
- Revision History
- Table of Contents
- Chapter 1 General Description
- Chapter 2 Interfacing the ISCC™
- Chapter 3 ISCC™ DMA and Ancillary Support Circuitry
- Chapter 4 Data Communication Modes
- Chapter 5 Register Descriptions
- 5.1 INTRODUCTION
- 5.2 REGISTER DESCRIPTIONS
- 5.3 SCC CELL REGISTER OVERVIEW
- 5.4 WRITE REGISTERS
- 5.4.1 Write Register 0 (Command Register)
- 5.4.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition)
- 5.4.3 Write Register 2 (Interrupt Vector)
- 5.4.4 Write Register 3 (Receive Parameters and Control)
- 5.4.5 Write Register 4 (Transmit/Receiver Miscellaneous Parameters and Modes)
- 5.4.6 Write Register 5 (Transmit Parameter and Controls)
- 5.4.7 Write Register 6 (Sync Characters or SDLC Address Field)
- 5.4.8 Write Register 7 (SYNC Character or SDLC Flag)
- 5.4.9 Write Register 8 (Transmit Buffer)
- 5.4.10 Write Register 9 (Master Interrupt Control)
- 5.4.11 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits)
- 5.4.12 Write Register 11 (Clock Mode Control)
- 5.4.13 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant)
- 5.4.14 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant)
- 5.4.15 Write Register 14 (Miscellaneous Control Bits)
- 5.4.16 Write Register 15 (External/Status Interrupt Control)
- 5.5 READ REGISTERS
- 5.6 DMA CELL REGISTER DESCRIPTIONS
- 5.6.1 Channel Command/Address Register
- 5.6.2 DMA Status Register
- 5.6.3 Interrupt Control Register
- 5.6.4 Interrupt Vector Register
- 5.6.5 Interrupt Command Register
- 5.6.6 Interrupt Status Register
- 5.6.7 DMA Enable Register
- 5.6.8 DMA Control Register
- 5.6.9 Receive DMA Count Registers A, B
- 5.6.10 Transmit DMA Count Registers A, B
- 5.6.11 Receive DMA Address Registers A, B
- 5.6.12 Transmit DMA Address Registers A, B
- 5.6.13 Bus Configuration Register
- Customer Support
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