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Clock
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Clock Guide
User manual for Clock
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Table of contents
Document Outline
Revision History
Preface
Table of Contents
List of Figures
List of Tables
1 Introduction
Figure 1-1: PCI-9527 Product Image
1.1 Features
1.2 Applications
1.3 Specifications
1.3.1 Analog Input
Table 1-1: Channel Characteristics
Table 1-2: Crosstalk
Table 1-3: Transfer Characteristics
Table 1-4: Analog Input Channel Bandwidth
Figure 1-2: Analog Input Channel Bandwidth, ±10 V Input Range
Table 1-5: AC Coupling
Figure 1-3: Magnitude Response of AC Couple of Input Channel
Table 1-6: Integrated Electronic Piezoelectric (IEPE)
1.3.2 Analog Output
Table 1-7: Channel Characteristics
Table 1-8: AO DC Accuracy
Table 1-9: Output Impedance
Table 1-10: AO Dynamic Characteristics
1.3.3 Triggers, Timebase
Table 1-11: Triggers
Table 1-12: Analog Trigger
Table 1-13: Digital Trigger
Table 1-14: Timebase
1.3.4 General Specifications
Table 1-15: Bus and Physical Specifications
Table 1-16: Environment Requirements
Table 1-17: Calibration
Table 1-18: Power Consumption
1.4 Software Support
1.4.1 Software Support
1.4.2 Programming Library
1.4.3 DSA-DASK
2 Getting Started
2.1 Installation Environment
2.2 Package Contents
2.3 Device Layout and IO Connectors
2.4 Installing the Module
2.5 Signal Connection
2.5.1 BNC Connector Polarity
2.5.2 Analog Input Connection
Table 2-1: Analog Input Connection
2.5.3 Analog Output Connection
Table 2-2: Analog Output Connection
3 Operation Theory
3.1 Functional Block Diagram
3.2 Analog Input Channel
3.2.1 Analog Input Front-End Configuration
Input Configuration, Differential or Pseudo Differential
Table 3-1: Input Configurations
Input Coupling, DC Coupling or AC Coupling
Input for IEPE
3.2.2 Input Range and Data Format
Table 3-2: Input Range and Data Format
3.2.3 ADC and Analog Input Filter
ADC (Analog-to-Digital Converter)
Table 3-3: ADC Sample Rates VS DSS Outpu Clock
Filter
3.2.4 FIFO and DMA Transfer For Analog Input
FIFO
Bus-mastering DMA Data Transfer
Figure 3-1: Linked List of PCI Address DMA Descriptors
3.3 Analog Output Channel
3.3.1 Analog Output Front-End Configuration
Output Configuration - Differential, Pseudo Differential
Table 3-4: Output Configuration
3.3.2 Output Range and Data Format
Table 3-5: Digital Input Code and Analog Output Range
3.3.3 DAC and Analog Output Filter
DAC (Digital-to-Analog Converter)
Table 3-6: DAC (Digital-to-Analog Converter)
Analog Front-End Filter
3.3.4 FIFO and DMA Transfer For Analog Output
FIFO
Bus-mastering DMA Data Transfer
3.4 Trigger Source and Trigger Mode
3.4.1 Trigger Sources
Figure 3-2: Trigger Architecture of the PCI-9527
Software Trigger
External Digital Trigger
Analog Trigger
Figure 3-3: Analog Trigger Conditions
3.4.2 Trigger Mode
Post Trigger Mode
Figure 3-4: Post-trigger Acquisition / Waveform Generation
Delay Trigger Mode
Figure 3-5: Delay Trigger Mode Acquisition / Waveform Generation
3.5 ADC and DAC Timing Control
3.5.1 Timebase Architecture
Figure 3-6: PCI-9527 Timebase Architecture
3.5.2 DDS Timing VS ADC/DAC Relationship
Table 3-7: Timing Relationship of the ADC, DAC and DDS Clock
3.5.3 Timing Constraint When AI and AO Enabled Simultaneously
3.5.4 Filter Delay in ADC and DAC
ADC Filter Delay
Table 3-8: ADC Filter Delay
DAC Filter Delay
Table 3-9: DAC Filter Delay
4 Calibration
4.1 Calibration Constant
4.2 Auto-Calibration
4.3 Offset Error Compensation During AI Sampling Rate Change
Table 4-1: Offset Compensation Time Required for Different Sampling Rates
5 Calibration
5.1 Loading Calibration Constants
5.2 Auto-calibration
5.3 Saving Calibration Constants
Important Safety Instructions
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