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5900 Guide
User manual for 5900
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Table of contents
Document Outline
1. Pin Descriptions
1.1 I/O Pin Characteristics
2. Typical Connection Diagrams
Figure 1. Typical Connection Diagram - Four Pseudo-Differential Analog Inputs
Figure 2. Typical Connection Diagram - Two Pseudo-Differential / Three Single-Ended Analog Inputs
Figure 3. Typical Connection Diagram - Six Single-Ended Analog Inputs
3. Characteristic and Specification Tables
Recommended Operating Conditions
Absolute Maximum Ratings
Analog Input Characteristics
Figure 4. CMRR Test Configuration
Figure 5. AINxREF Input Voltage Test Configuration
ADC Digital Filter Characteristics
HP Output Characteristics
Line Output Characteristics
Figure 6. HP Output Test Configuration
Figure 7. Line Output Test Configuration
Analog Passthrough Characteristics
Combined DAC Interpolation & On-Chip Analog FIlter Response
Switching Specifications - Serial Port
Figure 8. Serial Port Timing (Slave Mode)
Figure 9. Serial Port Timing (Master Mode)
Switching Specifications - I²C Control Port
Figure 10. I²C Control Port Timing
Switching Characteristics - SPI Control Port
Figure 11. Control Port Timing - SPI Format
Analog Output Attenuation Characteristics
DC Characteristics
Digital Interface Specifications & Characteristics
Figure 12. Power Consumption Test Configuration
Power Consumption - All Supplies = 1.8 V
Power Consumption - All Supplies = 2.5 V
4. Applications
4.1 Overview
4.1.1 Basic Architecture
4.1.2 Line Inputs
4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers)
4.1.4 Fixed-function DSP Engine
4.1.5 Beep Generator
4.1.6 Power Management
4.2 Analog Inputs
Figure 13. Analog Input Signal Flow
4.2.1 Pseudo-differential Inputs
Figure 14. Stereo Pseudo-Differential Input
4.2.2 Large-scale Inputs
Table 1. Input Voltage PGA Settings
Figure 15. Analog Input Attenuation
Table 2. Analog Input Design Parameters
Figure 16. Example Analog Input Attenuation
4.2.3 Microphone Inputs
Figure 17. MIC Input Mix w/Common Mode Rejection
4.2.4 Optional VCM Buffer
4.2.5 Automatic Level Control (ALC)
Figure 18. ALC Operation
4.3 Analog In to Analog Out Passthrough
4.4 Analog Outputs
Figure 19. DSP Engine Signal Flow
Figure 20. Analog Output Stage
4.5 Class H Amplifier
4.5.1 Power Control Options
Figure 21. Class H Volume-Adapt Paths
Figure 22. Volume Sum Effects
Figure 23. Channel/Amp Effect
Figure 24. HP/Line Channel Effects
4.5.2 Power Supply Transitions
Figure 25. VHPFILT Transitions
Figure 26. VHPFILT Hysteresis
4.5.3 Efficiency
Figure 27. Class H Power to Load vs. Power from VCP Supply - 32 W
Figure 28. Class H Power to Load vs. Power from VCP Supply - 16 W
4.6 Beep Generator
Figure 29. Beep Configuration Options
4.7 Limiter
Figure 30. Peak Detect & Limiter
4.8 Serial Port Clocking
Table 3. Serial Port Clock Ratio Settings
Figure 31. Serial Port Timing in Master Mode
4.9 Digital Interface Format
Figure 32. I²S Format
Figure 33. Left-Justified Format
4.10 Initialization
4.11 Recommended DAC to HP or Line Power Sequence
4.11.1 Power-Up Sequence
4.11.2 Power-Down Sequence
4.12 Recommended PGA to HP or Line Power Sequence (Analog Passthrough)
4.12.1 Power-Up Sequence
4.12.2 Power-Down Sequence
4.13 Control Port Operation
4.13.1 SPI Control
Figure 34. Control Port Timing in SPI Mode
4.13.2 I²C Control
Figure 35. Control Port Timing, I²C Write
Figure 36. Control Port Timing, I²C Read
4.13.3 Memory Address Pointer (MAP)
5. Register Quick Reference
6. Register Description
6.1 Device I.D. Register (Address 01h) (Read Only)
6.1.1 Device I.D. (Read Only)
6.2 Device Revision Register (Address 02h) (Read Only)
6.2.1 Alpha Revision (Read Only)
6.2.2 Numeric Revision (Read Only)
6.3 Power Control 1 (Address 03h)
6.3.1 Power Down VCM Bias Buffer
6.3.2 Power Down MIC Bias
6.3.3 Power Down ADC Charge Pump
6.3.4 Power Down ADC x
6.3.5 Power Down
6.4 Power Control 2 (Address 04h)
6.4.1 Headphone Power Control
6.4.2 Line Power Control
6.5 Clocking Control 1 (Address 05h)
6.5.1 Master/Slave Mode
6.5.2 SCLK Polarity
6.5.3 SCLK Equals MCLK
6.5.4 MCLK Pre-Divide
6.5.5 MCLK Divide
6.5.6 MCLK Disable
6.6 Clocking Control 2 (Address 06h)
6.6.1 Clock Ratio Auto-Detect
6.6.2 Clock Ratio
6.7 Serial Format (Address 07h)
6.7.1 CODEC Digital Interface Format
6.8 Class H Control (Address 08h)
6.8.1 Adaptive Power Adjustment
6.8.2 Charge Pump Frequency
6.9 Misc. Control (Address 09h)
6.9.1 Digital MUX
6.9.2 Analog Soft Ramp
6.9.3 Analog Zero Cross
6.9.4 Digital Soft Ramp
6.9.5 Freeze Registers
6.10 Status (Address 0Ah) (Read Only)
6.10.1 HPDETECT Pin Status (Read Only)
6.10.2 Serial Port Clock Error (Read Only)
6.10.3 DSP Engine Overflow (Read Only)
6.10.4 MIXx Overflow (Read Only)
6.10.5 ADCx Overflow (Read Only)
6.11 Playback Control (Address 0Bh)
6.11.1 Power Down DSP
6.11.2 HP/Line De-Emphasis
6.11.3 Playback Channels B=A
6.11.4 Invert PCM Signal Polarity
6.12 DSP Mute Controls (Address 0Ch)
6.12.1 ADC Mixer Channel x Mute
6.12.2 PCM Mixer Channel x Mute
6.12.3 Master Playback Mute
6.13 ADCx Mixer Volume: ADCA (Address 0Dh) & ADCB (Address 0Eh)
6.13.1 ADC Mixer Channel x Volume
6.14 PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h)
6.14.1 PCM Mixer Channel x Volume
6.15 Analog Input Advisory Volume (Address 11h)
6.15.1 Analog Input Advisory Volume
6.16 Digital Input Advisory Volume (Address 12h)
6.16.1 Digital Input Advisory Volume
6.17 Master Volume Control: MSTA (Address 13h) & MSTB (Address 14h)
6.17.1 Master Volume Control
6.18 Beep Frequency & On Time (Address 15h)
6.18.1 Beep Frequency
6.18.2 Beep On Time
6.19 Beep Volume & Off Time (Address 16h)
6.19.1 Beep Off Time
6.19.2 Beep Volume
6.20 Beep & Tone Configuration (Address 17h)
6.20.1 Beep Configuration
6.20.2 Treble Corner Frequency
6.20.3 Bass Corner Frequency
6.20.4 Tone Control Enable
6.21 Tone Control (Address 18h)
6.21.1 Treble Gain
6.21.2 Bass Gain
6.22 ADC & PCM Channel Mixer (Address 19h)
6.22.1 PCM Mix Channel Swap
6.22.2 ADC Mix Channel Swap
6.23 AIN Reference Configuration, ADC MUX (Address 1Ah)
6.23.1 Analog Input 2 x Reference Configuration
6.23.2 Analog Input 1 x Reference Configuration
6.23.3 ADC x Input Select
6.24 HPF Control (Address 1Bh)
6.24.1 ADCx High-Pass Filter
6.24.2 ADCx High-Pass Filter Freeze
6.24.3 HPF x Corner Frequency
6.25 Misc. ADC Control (Address 1Ch)
6.25.1 ADC Channel B=A
6.25.2 PGA Channel B=A
6.25.3 Digital Sum
6.25.4 Invert ADC Signal Polarity
6.25.5 ADC Mute
6.26 Gain & Bias Control (Address 1Dh)
6.26.1 PGA x Preamplifier Gain
6.26.2 Boostx
6.26.3 Microphone Bias Output Level
6.27 PGA x MUX, Volume: PGA A (Address 1Eh) & PGA B (Address 1Fh)
6.27.1 PGA x Input Select
6.27.2 PGAx Volume
6.28 ADCx Attenuator Control: ADCAATT (Address 20h) & ADCBATT (Address 21h)
6.28.1 ADCx Volume
6.29 ALC Enable & Attack Rate (Address 22h)
6.29.1 ALCx
6.29.2 ALC Attack Rate
6.30 ALC Release Rate (Address 23h)
6.30.1 ALC Limit All Channels
6.30.2 ALC Release Rate
6.31 ALC Threshold (Address 24h)
6.31.1 ALC Maximum Threshold
6.31.2 ALC Minimum Threshold
6.32 Noise Gate Control (Address 25h)
6.32.1 Noise Gate All Channels
6.32.2 Noise Gate Enable
6.32.3 Noise Gate Threshold and Boost
6.32.4 Noise Gate Delay Timing
6.33 ALC and Limiter Soft Ramp, Zero Cross Disables (Address 26h)
6.33.1 ALCx Soft Ramp Disable
6.33.2 ALCx Zero Cross Disable
6.33.3 Limiter Soft Ramp Disable
6.34 Automute, Line & HP MUX (Address 27h)
6.34.1 Auto Mute
6.34.2 Line Input Select
6.34.3 Headphone Input Select
6.35 Headphone Volume Control: HPA (Address 28h) & HPB (Address 29h)
6.35.1 Headphone Channel x Mute
6.35.2 Headphone Volume Control
6.36 Line Volume Control: LINEA (Address 2Ah) & LINEB (Address 2Bh)
6.36.1 Line Channel x Mute
6.36.2 Line Volume Control
6.37 Limiter Min/Max Thresholds (Address 2Ch)
6.37.1 Limiter Maximum Threshold
6.37.2 Limiter Cushion Threshold
6.38 Limiter Control, Release Rate (Address 2Dh)
6.38.1 Peak Detect and Limiter
6.38.2 Peak Signal Limit All Channels
6.38.3 Limiter Release Rate
6.39 Limiter Attack Rate (Address 2Eh)
6.39.1 Limiter Attack Rate
7. PCB Layout Considerations
7.1 Power Supply
7.2 Grounding
7.3 QFN Thermal Pad
8. Analog Volume Non-Linearity (DNL & INL)
Figure 37. PGA Step Size vs. Volume Setting
Figure 38. PGA Output Volume vs. Volume Setting
Figure 39. HP/Line Step Size vs. Volume Setting
Figure 40. HP/Line Output Volume vs. Volume Setting
9. ADC & DAC Digital Filters
Figure 41. ADC Frequency Response
Figure 42. ADC Stopband Rejection
Figure 43. ADC Transition Band
Figure 44. ADC Transition Band Detail
Figure 45. DAC Frequency Response
Figure 46. DAC Stopband
Figure 47. DAC Transition Band
Figure 48. DAC Transition Band (Detail)
10. Parameter Definitions
11. Package Dimensions
Thermal Characteristics
12. Ordering Information
13. References
14. Revision History
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